Hi,does anybody have a simple example of avalon streaming implementation? I have a system with huge amont of serial data and I want to use avalon streaming interface. simple example will give me an idea of starting point. thanks:)
Do you need to buffer the data in memory? I'm not sure what a good example would be since I'm not sure what you are trying to implement. The simplest example of streaming would be to hook up the output of a FIFO to the input of another FIFO if you just want to see how the streaming handshaking works.
Hi,Many thanks for your reply. I am currently developing an autonomous data acquisition vehicle for oil and gas pipelines. We have nearly 300 analog sensors which ADC modules control them. Every second I should collect nearly 1MB of data which all are in packets and serially is being transferred to the FPGA. I collect this data and write them to CF in FAT32 format or send it through Ethernet. I implement some templates which write data into DDR RAM directly. This will avid processor to access ram for a while. There is an option which I can either implement another Ram or processor. However, power consumption on this system is very critical and I don’t want to implement extra devices. As data from ADC to RAM are serial and are in packets so I think I can use the Avalon streaming for achieving higher performance. So you are right. I want to read data serially from ADCs and buffer it somewhere. I need more reliable algorithms for that. I was wondering if you give me something to start with as I have never used Avalon streaming before. For Ethernet I am not using the Avalon streaming either as I am using my own IP. If I am able to use Avalon streaming so I can increase the TCP/IP stack performance. Thanks, Aidin. :)
I think you want to use a DMA that accepts streaming data and writes it to memory which can then be sent later to flash or over Ethernet. There is a scatter-gather DMA that comes installed with the IP suite that gets used for various things like feeding streaming video to the screen or moving Ethernet packets back and forth in various designs that are installed with the Nios II EDS or on the Altera Nios II design examples page: http://www.altera.com/support/examples/nios2/exm-nios2.htmlHere is an alternative SGDMA that you might find suites your needs better called the modular SGDMA: http://www.altera.com/support/examples/nios2/exm-modular-scatter-gather-dma.html Here is an example of how I'm using it to implement dirt simple frame buffering to a streaming video pipeline: http://www.nioswiki.com/exampledesigns/modular_sgdma_video_frame_buffer Streaming is a really simple standard to use especially if you have no 'ready latency' Most of the time when I use streaming I use only three signals: data (payload data) ready (tells the data source that the sink is ready for data) valid (tells the data sink that the source is sending valid data) Data flows from the source to the sink in only one direction. Assuming that there is no ready latency then the handshaking is literally 'valid == 1' and 'ready == 1' --> move data. In other words the source says "here's some data" and the sink says "I'm ready for some data", when that case occurs the data moves from the source to the sink and the next 1+ cycles this all starts again. Ready latency makes things a little more complicated and it's intended to factor in latency into the handshake. You can read more about it here: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf Since you are working with ADC you will probably use FIFOs to provide buffering so if the FIFO is configured for lookahead mode then you shouldn't have any ready latency to deal with. *edit: I forgot about these too, I think DMAs would be better for you but just in case: http://www.altera.com/support/examples/nios2/exm-avalon-mm.html
Hi guys;I want to use SGDMA to buffer video streaming from a CVI, do you think that it is possible? I have an input of 1080P60. Please inform me if you have an idea about that. thanks. Rabie
--- Quote Start --- Streaming is a really simple standard to use especially if you have no 'ready latency' Most of the time when I use streaming I use only three signals: data (payload data) ready (tells the data source that the sink is ready for data) valid (tells the data sink that the source is sending valid data) --- Quote End --- That's great to hear! So I it is fine if I ignore the other signals in general? Thanks
It depends on what you need but usually that triplet of signals is all that's necessary. There are other signals in the Avalon-ST spec and depending on your needs you might need them:error: If you have to transport error information in the data stream channel: If you have to transport a channel number in the data stream (i.e. interleaved channels in the same physical stream of data) sop/eop: If you have to denote the start and end of a packet in the stream (for example if you were transporting Ethernet packets this would be handy) empty: If you need to denote unused symbols in the data stream. (for example if you were transporting 32-bit data of Ethernet packets you can use this to mark how many symbols are empty at the end of a packet if the packet isn't a multiple of four 8-bit symbols). Technically you can have an Avalon-ST port with just the data port but in general streams usually don't transfer data every clock cycle or have to backpressure so that's why you typically include ready and valid. The Avalon-ST protocol is very flexible just like Avalon-MM so there are very few mandatory signals to include.
--- Quote Start --- Technically you can have an Avalon-ST port with just the data port but in general streams usually don't transfer data every clock cycle or have to backpressure so that's why you typically include ready and valid. --- Quote End --- Thanks for your response! I just had one more question: how much data exactly is transferred each clock cycle? One symbol?
It's as many symbols as you want. Symbols are similar to bytes in Avalon-MM where it's a unit of data. So you could have for example a 32-bit data port that has four 8-bit symbols, two 16-bit symbols, or a single 32-bit symbol for example (could even have 1-bit symbols although that's usually not useful). Every transfer of data (valid = 1 and ready = 1) the full width of the data is transferred which will be one or more symbols. The restriction is that the data width must be a multiple of the symbol size, or in other words DATA_WIDTH mod SYMBOL_SIZE must equal 0.If you are designing a streaming block that needs to hook up to some other streaming block, I recommend taking a look at the symbol size of other block. If you took two 32-bit streaming ports, one of which uses 8-bit symbols and another that uses 16-bit symbols Qsys won't be able to connect them. So if you check ahead of time on the symbol size you can save yourself work later one making gaskets that adapt one symbol size to another.
Thanks BadOmen for the great response!That makes sense. If I am writing to an on-chip memory where each memory cell is a byte, Qsys tells me that the memory's Avalon-MM slave input has symbol width of 8, because each cell is 8 bits. Therefore my signal coming into that memory must also have a symbol width of 8.
That's correct, Avalon-MM even has a concept of symbols. 99.9999999% of the time a symbol will be 8 bits (byte) but the reason why even the memory mapped standard supports non-eight bit bytes is for things like transporting parity or ECC information along with the data.In general if you are moving data between Avalon-ST and Avalon-MM (i.e. a DMA) then usually you use the same symbol size. If you are moving data between ST and MM pay close attention to symbol ordering because most ST IP has the least significant symbol in the MSBs (some people call this big endian.... but 'network order' is the more appropriate name for it) while MM IP is little endian. Some IP blocks are written without the developer knowing about this which can lead to symbols getting flipped around between the two domains.