Avalon on a backplane ??

[Altera_Forum]

Hello,  

 In my current project, I'm thinking about using an architecture with one FPGA Card which hosts the Nios 2 processor and some CPLD cards which host some specific VHLD slave funcions. Moreover, I'm thinking about interconnect the Master Card (FPGA Card) and the Slave Cards (CPLD Cards) using a standard backplane which will transit the Avalon Bus, 3.3V, GND, IRQ ....  My questions are :  Is it possible to make the Avalon Bus transit on a backplane ? Do you know any mechanical standard I could use as a backplane (cPCI for example) ? Do you know the electrical specification for an extern Avalon Bus ?  Thank you.  Nicolas.

[Altera_Forum]

- Yes, it's possible. Check out the Avalon-MM tri-state bridge. 

 - Any with enough pins for all the signals you'll need and a bus topology: PCI, cPCI, VME, etc  - There is none, you can use anything that supports tri-state operation.

[Altera_Forum]

There are a few trade-offs to consider. One is the overall bandwidth. If the CPLD cards are have a reasonable low throughput and you do not have many of them, say 8 pcs or so, a general bus is feasible. On the other hand if you have a large IO throughput you may be better off to connect the CPLD cards in a star fashion where every CPLD board has its own dedicated high-speed channels to and from the main FPGA-board. Another option is to daisy-chain the bus, where every card retransmits the signals left and right. 

The other one is signal integrity. This is much harder for a bus than for point to point connections, especially if you have to achieve a high throughput. Point to point connections can use series termination, either incorporated in the IO-cell of the FPGA, or just a small external 39 ohm resistor. A bus needs parallel termination at both sides, presenting a 25 ohm load to drive by the cards. Bear in mind that not the frequency of the clock is dominant but rather the rise and fall times of the signals. Modern FPGAs are fast things with fast edge rates ... So you have to make nice impedance controlled boards and use suitable connectors. Point to point systems can use Source-Synchronous signalling where a broadside bus needs a master clock defining all transactions. But at a low clock speed this is quite manageable. In stead of using a CPLD on the slave cards, I assume you are thinking of using MAX II devices, it may be a better idea to use small Cyclone III or IV devices and load/configure these from the master FPGA board.

[Altera_Forum]

Thank you for your answers. 

 My application doesn't need a high throwput because the Master will only have to send commands to and receive status from the slaves cards. However, the clock in the FPGA which wll driver the Avalon bus is 25 MHz so like Josyb said, I have to worry about signal integrity. Josyb, do you have any advice for nice impedance controlled boards and suitable connectors for this application. For connectors, I thought about using cPCI connector but I don't know how to do the impedance adaptation on the master Bord and on the slave boards.  To my mind, as there is only 1 Master and that the Avalon bus offer one Data Bus for write operation (writedata) and one Data Bus for read operation (readdata), I think that I only have to implement a tri-state register in the Slave CPLD on the readdata bus. I have posted a JPG file of the topology of the bus. Do you agree with this ?  Finally, have you heard about any previous project that have chosen this architecture with a Avalon Bus in the Backplane. Maybe, any revendors of FPGA board that can be usefull for me for this application of Avalon Backplane.  Nicolas.

[Altera_Forum]

You can tun the external bus at a lower frequency, just stick a clock crossing bridge in your SOPC. 

 On the external bus, you can also use the same lines for read-data and write-data.  For some reason, the Avalon specificatio no longer documents MM tristate masters and slaves. But the options are still available in SOPC.  You can also ditch Avalon for the external bus completely. Just write your own bridge.

[Altera_Forum]

--- Quote Start ---  Thank you for your answers.  My application doesn't need a high throwput because the Master will only have to send commands to and receive status from the slaves cards. However, the clock in the FPGA which wll driver the Avalon bus is 25 MHz so like Josyb said, I have to worry about signal integrity. Josyb, do you have any advice for nice impedance controlled boards and suitable connectors for this application. For connectors, I thought about using cPCI connector but I don't know how to do the impedance adaptation on the master Bord and on the slave boards.  To my mind, as there is only 1 Master and that the Avalon bus offer one Data Bus for write operation (writedata) and one Data Bus for read operation (readdata), I think that I only have to implement a tri-state register in the Slave CPLD on the readdata bus. I have posted a JPG file of the topology of the bus. Do you agree with this ?  Finally, have you heard about any previous project that have chosen this architecture with a Avalon Bus in the Backplane. Maybe, any revendors of FPGA board that can be usefull for me for this application of Avalon Backplane.  Nicolas.  --- Quote End ---   Basically your jpg shows a workable set-up. I tend to side with rbugalho and also recommend to use a 'proprietary' bus system and to try to minimize on the number of connections. You then can have a smaller backplane with smaller connectors. The controlled impedance is by design: use a 6 or 8 layer pcb and lay out buried (assymetic) striplines and aim at the smallest reasonable width of the tracks. This will get you an impedance between 50 and 100 ohms, the higher the better. You need to 'parallel terminate' the write data and addresses coming from the main FPGA at the far bus side with a resistor of the value obtained in the layout. The read data has to 'parallel terminated' with this value on both sides of the bus. You should check if the CPLD has enough output current to drive the lines. The cPCI connectors you mention are perfectly usable in your setup. In theory you have to match the impedance of your tracks to the values stipulated for the connector, so you may have to layout the board for possibly 50 or 60 ohms characteristic impedance.

[Altera_Forum]

OK for the signal integrity. 

Another question is about the topology of the bus I proposed : Is there a problem to use the Avalon Bus which is the processor Bus (transmit data between processor and his external SRAM) to access to the slave cards (as an extension bus in reality) ? Unless, I would rather use 2 Avalon Master MM : One for Bus Processeur (Nios2, UART, SRAM, GPIO, ...) and 1 for extension bus through the backplane ? Is it a better solution ?  Actually, a more conventional solution would use the Avalon bus as the processor Bus and have a Brige Avalon - PCI for example to access the slave cards ? However, it complicates my design .... Some comments, please ...  Nicolas.