BGA Socket Adapters? or 2 FPGAs connected?

[Altera_Forum]

Hi guys, 

 I'm doing a university project. I trying to design a board and i'm running into the problem of limiting pins and logic element counts.   The university can only mount flat pack style stuff and can't do ball grid arrays. The only cyclones that come close is the 240 pin 39K elements. But apparently only 128 usable IO. I need more pins!!   So has anyone been down either of these paths? 1. Use a ballgrid socket adapter to allow mounting and easier install? 2. Have two FPGAs in the one datapath?   Anythoughs and recommendations will be greatly appreciated.

[Altera_Forum]

http://www.mill-max.com/products/newproducts_detail.cfm?pid=7 

 his is the only kind of "BGA socket" I've heard of. The socket is itself BGA and the BGA device also needs to be soldered to a adapter. So, I don't think it will help you.  Using two FPGAs is possible, but you need to be careful about splitting your design because I/Os are slow.

[Altera_Forum]

AsValdr, 

there are a lot of BGA sockets in the market, but that is not the big point. Do you really need a selfmade design; is this a required part of your task ?  Why not working with a ready-to-use board ? (made by experienced PCB designers/electrically tested/ re-usable for other projects/...)  Regards, Michael

[Altera_Forum]

--- Quote Start ---   I'm doing a university project. I trying to design a board and i'm running into the problem of limiting pins and logic element counts.    --- Quote End ---  What is your project supposed to implement? With that information, you can get recommendations on existing boards, or on board design.  Screaming Circuits and Advanced Assembly can load BGAs on boards, so its not something your university really needs to be able to do, ultimately it will come down to how much $ you are willing to spend (and your location).  Cheers, Dave

[Altera_Forum]

Thanks guys, 

 What i'm making is a video over ethernet boards and need the following devices:   (gpio) 40 pins : Terasic D5M Camera (For TX board) or Terasic LTM Screen for the (RX Board).   ~57 Pins: SDRAM 32bits wide. To copy the DE2-115 i would be using 2x64mb chips.   ~47 Pins: Ethernet (use the SMSC LAN91C111)   _____________________________ Total of 144 Pins. (I'd likely need more fo tidbits here and there)   Thats a minumum, i would like more for a VGA chip, but i'll have to perhaps run that on the GPIO.   I was looking at using the EP3c240. Which is 240pin with apparently only 128 usable IO. I hope the programming pins are in those excess pins. Is there seriously 112 power, gnd and reserved pins? _________________________________________   I'm in Australia in the case of talking about location

[Altera_Forum]

--- Quote Start ---   What i'm making is a video over ethernet boards and need the following devices:   (gpio) 40 pins : Terasic D5M Camera (For TX board) or Terasic LTM Screen for the (RX Board).   ~57 Pins: SDRAM 32bits wide. To copy the DE2-115 i would be using 2x64mb chips.   ~47 Pins: Ethernet (use the SMSC LAN91C111)    --- Quote End ---    What is wrong with using a Terasic board for the FPGA too?    --- Quote Start ---   I'm in Australia in the case of talking about location  --- Quote End ---    Have you checked board assembly prices? You might be surprised how reasonable they are.   Cheers, Dave

[Altera_Forum]

Why do You need so much RAM? Are You placing a video frame buffer there?

[Altera_Forum]

I was originally planning to use it as both a frame buffer and for the Nios core running ethernet. 

I'm unsure of how much i can get away with. I imagine i'll need to keep it 32 bits wide. socrates, your working on something similar? how much ram are you using?   I require to get it off the development boards so as to achgeive the required complexity, plus its something i want to do if its possible.   2 fpgas In regards to this, as it is now on my De2, i have the camera feeding pixels at 50Mhz. This would mean that the IO is fast enough to handle that. So is it possible that i connect two fpgas using a avalon ST bus style connection. (32 data pins + 5 or so control signals) Having just the ethernet, and SDRAM on one FPGA and the other has the auxiliaries. This could mean that i use 2 160 pin FPGAs (15K LEs each). Am i crazy?

[Altera_Forum]

I use only one SDRAM chip and it is used only for Nios. All the video data fits to 4kb FIFO, which is encapsulated to UDP or RTP packets and sent over ethernet. My recent tests with 62-63Mbps video from satellite runs without any single error. I don't have any faster source to test the performance, but I suppose it should run up to 90Mbps without problems.

[Altera_Forum]

Remember a while we discussed our approaches with UDP. I went the hardcoded UDP MUX; i haven't developed a way to properly measure speed; but my system drops packets unless i'm on a Gigabit network. 

THis means i must be exceeding the 100Mbps. Though i can't fully test speed as I haven't tried cranking it up to have no breaks between packets. Too many tasks on the go for em atm and time is ticking.   What SRAM chip are you using? Size and data width. Are you using an SMSC ethernet chip? What width data bus are you using?

[Altera_Forum]

No, it's Marvell 88E1111 on RGMII bus. capable of 1GbE, but I have 10/100 switch only, so it auto-negotiates to 100Mbps max. 

 I use SDRAM, not SRAM.