Beginner questions on HDL component mapping

[Altera_Forum]

Hello, 

 I have a couple of confusing points about component port mapping, which I would really appreciate some explanation on.   1) Do the inputs map to inputs only? Can an output of a component be mapped to a port declared in the Entity as an input?   2) What does it mean when a signal is mapped to more than one component? For example, I have,   ARCHITECTURE arch of ent IS .... signal CLK: STD_LOGIC; ....   BEGIN   component1: ENTITY work.PLL PORT MAP ( OUTCLK => CLK );   ... ...   component2: ENTITY work.CLKOUT PORT MAP ( CLKOUT => CLK );   ... END ARCHITECTURE arch     In this case, what does it mean to have two clocks mapping to one input? The code is concurrent, so what effects does it have when two mapping to one signal?     Thank you very much.

[Altera_Forum]

Your example doesn't fit your question. CLK isn't a port in the entity, it's a signal. 

 If the CLK ports would be outputs at both components, you get a "multiple driver" error. The signal CLK can have only one driver. Please consider that VHDL is a hardware description language. The design must be implementable in hardware. Try to draw a hardware logic circuit representing your VHDL design. Where is each signal originated from and where goes it to?  P.S.: Without knowing the component declarations, it's unclear what the above example means.

[Altera_Forum]

Thank you FvM. 

 Sorry I have made a mistake. The code considers a signal, CLK, being mapped to outputs of two components. I am confused as to what happens in this cae and why would you use such multiple mapping.   Thank you.

[Altera_Forum]

--- Quote Start ---  Thank you FvM.   Sorry I have made a mistake. The code considers a signal, CLK, being mapped to outputs of two components. I am confused as to what happens in this cae and why would you use such multiple mapping.   Thank you.  --- Quote End ---    Basically, for clocks, you wouldnt  Allowing multiple drivers allows you to model tri-state buffers. These do not exist internally on a FPGA, but do exist on output pins.  For example if you did this:  sig <= '1'; sig <= '0';  In simulation you would see 'X' (Unknown) and the synthesisor would give you an error talking about multiple drivers on "sig"  Whereas if you did this:  sig <= 'Z'; sig <= '1';  in simulation sig would be '1' and systhesis would be fine.  Tri state buffers are used on inout ports. The inout port type should only be used at the top level. example below:   port ( data_port : inout std_logic_vector ); ...... --tri-state buffer dat_port <= (others => 'Z') when read_en = '1' else output_data; --input register process(clk) begin if rising_edge(clk) then if read_en = '1' then input_data <= data_port; end if; end if; end process;

[Altera_Forum]

--- Quote Start ---  Basically, for clocks, you wouldnt   Allowing multiple drivers allows you to model tri-state buffers. These do not exist internally on a FPGA, but do exist on output pins.     --- Quote End ---     Thank you very much Tricky. You just explained a "multiple driver" error I have been getting and had no idea what I was doing. Thank you for that.   I am still a little confused about multiple mapping. Could you tell me what would happen if I do this multiple mapping the other way. For example,  ARCHITECTURE arch of ent IS .... signal CLK: STD_LOGIC; .... BEGIN component1: ENTITY work.LED_FLASHER PORT MAP ( LEDCLK => CLK ); ... ... component2: ENTITY work.LED_FLASHER PORT MAP ( LEDCLK => CLK ); ... END ARCHITECTURE arch    What would happen in this case if I do multiple mappings to a component port?   Thank you very much for all the input.   Cheers.

[Altera_Forum]

Component instantiation is just another way of assigning signals in concurrent code. The same rules apply, that are valid for other signal assignments. I guess, CLK is an input port, your example doesn't state this explicitely. Of course, you can drive as much instances from the same signal, as you like to. Typically, system-wide clock and reset drive out to all components in a design.

[Altera_Forum]

Thank you very much FvM. I'm a little more confused to be honest. So the code I am examining has something like this: 

  ARCHITECTURE arch of ent IS .... signal someSignal1: STD_LOGIC; signal someSignal2: STD_LOGIC .... BEGIN component1: ENTITY work.LED_FLASHER PORT MAP ( LEDCLK = someSignal1; LED=> led_number1 ); ... ... component2: ENTITY work.LED_FLASHER PORT MAP ( LEDCLK => someSignal2, LED => led_number2 ); ... END ARCHITECTURE arch    So I have tewdifferent signals mapping to LED_FLASHER, LEDCLK and LED. First is an input and the second is an output. Basically one output 'LED' is used to drive two led's (led_number1 and led_number2). Think of someSignals as two different clocks. And the LED's are flashed according to these clocks.   So when someSignals are mapped concurrently, how would this operate? Why wouldn't this create a multiple driver error?   Some explanation or a reference is very much appreciated.   Cheers.

[Altera_Forum]

You have to think about signal direction.  

 you are connecting "someSignal" to an input of LED_FLASHER. Basically 1 clock is connecting to multiple destinations. That is fine.   When is not fine is when you try and put lots of different things into 1 signal.   Basically, what you are trying to do is this:   _____________ | | clk------> | LED_FLASHER | --------> led_number1 | |_____________| | | | _____________ | | | `---> | LED_FLASHER | --------> led_number2 |_____________|

[Altera_Forum]

--- Quote Start ---  You have to think about signal direction.   you are connecting "someSignal" to an input of LED_FLASHER. Basically 1 clock is connecting to multiple destinations. That is fine.   When is not fine is when you try and put lots of different things into 1 signal.   Basically, what you are trying to do is this:   _____________ | | clk------> | LED_FLASHER | --------> led_number1 | |_____________| | | | _____________ | | | `---> | LED_FLASHER | --------> led_number2 |_____________|   --- Quote End ---     Thank you very much once again Tricky. What's happening in the code is something like: _____________ | | clk1------> | LED_FLASHER | --------> led_number1 |_____________| _____________ | | clk2------> | LED_FLASHER | --------> led_number2 |_____________|   --- Quote End ---    I cant understand what would happen in this case. There is only one input and one output in LED_FLASHER. And the program is using this to flash TWO leds using TWO clocks.  Thank you again.

[Altera_Forum]

There is no problem. In VHDL you instantiate entities. You can instantiate each entity as many times as you want and drive them from different signals. They are completly independent. 

 So in your case, its exactly like you said - 2 separate clocks drive 2 separate LEDS. there is only 1 source file for LED_FLASHER. You dont need 2 source files.

[Altera_Forum]

--- Quote Start ---  There is no problem. In VHDL you instantiate entities. You can instantiate each entity as many times as you want and drive them from different signals. They are completly independent.  So in your case, its exactly like you said - 2 separate clocks drive 2 separate LEDS. there is only 1 source file for LED_FLASHER. You dont need 2 source files.  --- Quote End ---    Thank you soo much Tricky!! Instantiating two different entities! thats what happening here.. their behavior is independent..  Appreciate all the help mate... thanks a bunch for clearing that out..