Better to use a PLL or a counter (HW question)

[Altera_Forum]

Hi , 

 I'm wondering if it is better to use a PLL or a counter to devide a clk for lower freq?    Regards,

[Altera_Forum]

PLL is generally better and easier. 

PLL is almost mandatory if you want to use the generated frequency to clock other devices.  You can think to use a counter only if your lower frequency is a generic signal not intended to clock anything and if you are low on PLL resources. Otherwise it is worth "wasting" a PLL output.

[Altera_Forum]

You should never never divide a clock in logic, always use a PLL. Then in logic create clock enables to move data around at the "lower frequency"

[Altera_Forum]

Cris72 is right. A few other points: 

A PLL output requires a global resource. This is good for timing(since it is low skew to all destinations and will be low skew in relation to other outputs of the PLL). This is also bad since it uses a global. You might be running low on them and they take up power, so if your ripple clock only feeds 10 registers or something like that, it's something of a waste. Also, timing constraints are a little more difficult with a ripple clock. You have to put a generated clock constraint on the register, and have the -source be the node that drives it(presumably a PLL output or input port). If you have multiple ripple clock registers(i.e. a /2 register feeding another /2 register feeding another one) then each stage needs a generated clock. (If it's just a large counter and you use the MSB or something like that, then only the MSB needs the generated clock, since it is directly driven by the main clock)

[Altera_Forum]

There is nothing wrong in using a counter to divide a clock, as long as there are no transfers between both clocks. Furthermore, it is much easier to gate and to change the frequency at runtime.

[Altera_Forum]

Thx all for the replies.  

 @ Rysc -> not all you r saying is clear to me.  I just startet with TimeQuest Analyzer and timing constraints.   I have another question but i'll make it in another topic. Thx

[Altera_Forum]

Hey Chris! 

 We want to load an Image in SRAM and we want to perform segmentation algorithm on the loaded image and siplay it on the VGA Screen. We want to implement this objective on NIOS platform using SOPC builder.   Could you please tell us in what way the above objective can be accomplished. If it is possible please send us any related reference design or any pre-generated hardware platform(SOPC Builder) for image processing.  Thanks Chris