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Hi,
Is it possible to have bidirectional differential IO's in Altera FPGA. (Any series). Plz reply. Regards, JaseelLink Copied
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As far as I understand, only differential SSTL is supported for memory. Particularly no output enable is provided for any LVDS standard, so anything similar to M-LVDS isn't supported. For lower bit rates, a pseudo differential driver using two outputs and separate LVDS receiver could probably be used.
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