Bidirectional buffer

[Altera_Forum]

Hi, 

 I am working on Altera FPGA. Please help me to code a Bidirectional bus using HDL. Can anyone share a code for this.  Regards, freak

[Altera_Forum]

which HDL? AHDL, VHDL or Verilog?

[Altera_Forum]

For example, this could be a sample code for VHDL 

(I wrote it without checking for syntax errors, be warned)   entity io_buffer is  port ( data_out : in std_logic_vector(WIDTH-1 downto 0);  data_in : out std_logic_vector(WIDTH-1 downto 0);  data_out_ena : in std_logic;  io_data : inout std_logic_vector(WIDTH-1 downto 0) ); end io_buffer;  architecture arch of io_buffer is begin  bidir_buffer : process (data_out_ena, io_data)  begin  if (data_out_ena = '1') then  io_data <= data_out;  else   io_data <= (others => '0');  end if;    data_in <= io_data;     end process bidir_buffer; end arch;

[Altera_Forum]

I think you meant 

 io_data <= (others => 'Z');

[Altera_Forum]

Sorry. You are right, Tricky. 

As I said I wrote the code without checking

[Altera_Forum]

Thanks Triky, Cris. 

 Can i use the same code if i target for FPGA and ASIC. My doubt is, do i need to modify 'Z' if using in either ASIC or FPGA.  Regards, freak

[Altera_Forum]

You can use Z for either, since HDL simply describes how your system must behave. 

Z means that signal is not driven, just like a tristate output. How the described function is actually synthesized into the device depends from the synthesis tool and on device cababilites: i.e. if the real device has tristate buffers available, a true tristate bus can be generated; otherwise the same behaviour could be implemented with logic gates if the bidir bus is internal to the device and other bus drivers are known.

[Altera_Forum]

Hi Cris, 

 If i have tristate buffers in my code, will Quartus-II automatically targets to Tristate buffers in Altera devices. Please comment.  Regards, freak

[Altera_Forum]

It should do if you have followed the coding guidelines for tristate buffers. The modified code cris posted should be ok.

[Altera_Forum]

Note that FGPAs only support tri-state bufers for I/O signals. 

 There is no tri-state capability for internal signals. However, if you use tri-state driven internal signals, Quartus will try to reproduce the behavior using multiplexers.

[Altera_Forum]

Hi, I have a case similar to the code above. However, during gate-level simulation, while io_data has 'Z' values, data_in has 'X' value when data_out_ena is not '1'. What could probably cause the simulation to be behaving in this way?

[Altera_Forum]

'X' means the signal has an undefined state. This is because when data_out_ena = '0', io_data is tristated and it's supposed to be driven by an external source. If you dont' specify any external signal, data_in state is indeed undefined.

[Altera_Forum]

Thanks Cris72 for the feedback. 

 However, I have already defined my io_data to be 'Z' in the testbench but the problem is the data_in is 'X' instead of Z when in tri-state condition. Any other possible root cause?

[Altera_Forum]

AFAIK the tristate condition only applies to output drive: the actual signal state depends on other active drivers and in the real world it always switches either low or high according to the physical behaviour of logic gates (CMOS, TTL, presence of pullups or pulldown...). In any case the real signal always falls into a specific state, low or high: there is not a 'tristate' level. 

Without an explicit specification, the simulator can't determine what the real signal status will be, then it indeed place it as 'undefined'

[Altera_Forum]

--- Quote Start ---  In any case the real signal always falls into a specific state, low or high.  --- Quote End ---   Not necessarily. A floating pin without pull/up, pull-down or hold circuit might also arbitrarily oscillate between '1' and '0'. 'X' in simulation can be understood as reflecting this unknown state.    --- Quote Start ---  there is not a 'tristate' level.  --- Quote End ---   That's the essential point. 'Z' can't be detected as an input state.