Bidirectional pins in schematic entry

[Altera_Forum]

I am attempting to connect to a nand flash device with shared input/output data and command pins. I am using schematic entry for my Quartus top level design and I have added bidirectional pins that connect to ALT_IOBUF buffers. The output of these buffers looks to be controlled with an enable signal. My questions are: 

 1) is this the correct way to implement bidirectional pins in schematic entry?  2) does vcc or gnd enable the output buffer?  3) is there any kind of direction control necessary for the pin itself?  4) if not (which there is nothing evident in the schematic pin symbol) does a bidirectional pin just perform as a simple wire between the ALT_IOBUF buffer and my circuit board and it is up to me to control what source is driving the signal on the pin?

[Altera_Forum]

--- Quote Start ---   1) is this the correct way to implement bidirectional pins in schematic entry?   --- Quote End ---   Yes, it is.    --- Quote Start ---  2) does vcc or gnd enable the output buffer?   --- Quote End ---   ALT_IOBUF standard configuration is with active high output enable (OE).  That means when OE=1 IO port will drive data present on I input, while when OE=0 IO port behaves as an input. Accessing ALT_IOBUF properties you can even change the OE polarity.    --- Quote Start ---   3) is there any kind of direction control necessary for the pin itself? 4) if not (which there is nothing evident in the schematic pin symbol) does a bidirectional pin just perform as a simple wire between the ALT_IOBUF buffer and my circuit board and it is up to me to control what source is driving the signal on the pin?  --- Quote End ---     --- Quote End ---   Yes. In order to create a true bidirectional port, your internal logic must provide 3 signals: output, input and direction (i.e. OE) The same must be accomplished by external circuitry. So it is mandatory you need some kind of logic or arbitration to avoid signal contention, namely fpga pin can behave as an output only when the external device is not driving the signal itself. Usually the same internal OE signal is used (possibily inverted) to enable the external device driver. The typical usage is for connection to flash or sram memory:  ALT_IOBUF - IO connected to any memory data pin (bidirectional)  ALT_IOBUF - OE routed to an output pin of fpga and connected to RDn on external memory device

[Altera_Forum]

Thanks for the feedback Cris. This does appear to be working in my design now.

[Altera_Forum]

All, Sorry about posting to this post, thought I was posting to my original.. 

but.... I figured out my problem.  I didn't set my bi-pin to anything. After I set them to an UNKNOWN input, then the simulator was able to produce the correct output I was expecting.  Keith