Hi guys! I'm using Cyclone V FPGA and have some probles with timing. There are some faling path with IC delay above 11ns (it's seem that this the reason). In my design I use 2 clocks: 100MHz and 200MHz. Both of them are generated from one quartz:QUARTZ ----> EXT_PLL----> FPGA_PIN_A (CLK_A)----->INT_PLL_A(200MHz) |---------->FPGA_PIN_B(CLK_B------>INT_PLL_B(100MHz) In SDC file I constrained both clocks (CLK_A and CLK_ B as base clocks and have used derive_pll_clocks to constrain internal PLLs. Clk 200 MHz is used for IF signal generation and some internal synchronization. Clk 100MHz is used for transmition data over JESD204. The problem is in clock crossing logic. COMB---->REG_A 200 MHz -----> REG_B 100 MHz ------> COMB IC delay between REG_A and REG_B > 11ns. I this it's rather big value, but I have no idea to fix it. http://www.alteraforum.com/forum/attachment.php?attachmentid=12335&stc=1
You can resolve this problem using "set_malticycle_path end" constraint for SDC to set both setup and hold edge.set_multicycle_path -end -setup -from [get_cells FF1] -to [get_cells FF2] N set_multicycle_path -end -hold -from [get_cells FF1] -to [get_cells FF2] N-1 or using more than 2 FFs in this path, and set false_path constraint to SDC.