BlockRAM performance for 2.3Gs/s DDS AWG

[Altera_Forum]

Which of the Altera products has sufficient BlockRAM performance to be suitable for a DDS AWG data source for the MAX5879 DAC (14bits @ 2.3Gsps) ? 

  The data generated in the FPGA should update this DAC at 2.3Gs/s from on chip BRAM holding arbitrary waveform samples and addressed by 20 most significant bits of a 48-bit phase accumulator.   I don't expect for someone to make the device selection for me, but I would appreciate any advice what to look for in the data sheets in order to make sure that the above feat is achievable.    George

[Altera_Forum]

--- Quote Start ---  Which of the Altera products has sufficient BlockRAM performance to be suitable for a DDS AWG data source for the MAX5879 DAC (14bits @ 2.3Gsps) ?    --- Quote End ---  Its not the RAM you need to care about, its the I/O interface.  From the Maxim web page:  the device has four 14-bit, multiplexed, low-voltage differential signaling (lvds) input ports that each operates up to 1150mwps.  So you need an FPGA with 1.15Gbps LVDS. The Stratix series devices can operate at this data rate, so you will need to use one of them.  Here's a design that uses 1Gbps to an ADC interface. The DAC will be similar:  http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)  Cheers, Dave

[Altera_Forum]

Assuming that the I/O problems are solved somehow, I still do not understand how is it possible for a 2ns BRAM to feed the I/O subsystem at 2.3Gs/s. 

 Even if I "go wide" how can I have the data retrieved from the BRAM faster that 600Ms/s for arbitrary Frequency Tunning Words (FTW) ?  In DDS the SRAM access is sequential, but it happens at arbitrary address increments...

[Altera_Forum]

--- Quote Start ---  Assuming that the I/O problems are solved somehow, I still do not understand how is it possible for a 2ns BRAM to feed the I/O subsystem at 2.3Gs/s.  Even if I "go wide" how can I have the data retrieved from the BRAM faster that 500Ms/s for arbitrary Frequency Tunning Words (FTW) ?  In DDS the SRAM access is sequential, but it happens at arbitrary address increments...  --- Quote End ---    Work backwards from the output;  * 14-bit output at 2.3GSps * 2 x 14-bit LVDS signals, double data-rate, at 1.15GSps * LVDS transmit serialized in say x8 mode, sending bits to 14 LVDS channels, at 1.15/8 = 143.75MSps * 14 x 8-bit width or 8 x 14-bit RAMs for the sample look-ups  The FPGA logic needs to implement a decimated NCO, where the decimation factor is the LVDS serialization factor. The decimation ultimately means you have to duplicate the NCO logic in the FPGA, so that you can simultaneously 'look-up' multiple NCO entries for a given FTW, and then serialize those entries.  To understand the concept, start off with an NCO driving a DAC at Nyquist rate. The try a demux-by-2 setup, then demux-by-4, etc. The pattern of logic will become clearer.  Cheers, Dave