Board design using Cyclone V

[Altera_Forum]

I have a number of questions regarding hardware for FPGA boards that may or not be answered here.  

 having designed my own board from scratch I have a number of issues or questions: The device is cyclone V with EPCS128 config device, JTAG ASDI and a number of peripheral interfaces. ENETs, ADC DAC, etc.  1.) I can program the config device by ASDI but it is slow. I can program and debug the FPGA using JTAG but I can not program the config device by the JTAG as I have with past board designs. It runs to 90% full or more and fails a percent or two before the end. Does anyone have any experience of this?  2.) My board functions fine appart from the above but gets very very hot. All functions and interfaces work fine, all supply rails are fine. Is this usual for a cyclone V with 300,000 LES and only 40,000 in use clocked at 50MHz? Im guessing its 40 degrees C.  3.) when clocking out of the PLL output lines I have requirements to clock 3.3V and 2.5V do I need to set the bank voltage for this pin to select this or can I change it in Quartus.  4.) When communicating with pll outputs and clock inputs on differential 3.3v what levels should I expect? 0V to 3.3V in phase and out? On one clock input I currently have -400mv to plus 3.6V and I can not find out why. the device feeding the signals in is set to 3.3V and bar a series DC blocking capacitor ( I know this generates negative volts ) I should still have 3.3V max! this may make my FPGA sick.   5.) If using LVDS clocking inputson dedicated clock pins do I have to set the whole bank to these voltage levels? It woudl be good in future designs to reduce clock jitter by using a better standard than single ended 0-3.3v clock or differential 3.3v clock.   Thankyou all for your support.  Rob

[Altera_Forum]

"2.) My board functions fine appart from the above but gets very very hot. All functions and interfaces work fine, all supply rails are fine. Is this usual for a cyclone V with 300,000 LES and only 40,000 in use clocked at 50MHz? Im guessing its 40 degrees C." 

 40 degrees C should be still with the device's operating specs. For commercial part, if I remember it correctly, the temperature supported is 0-85C. So, 40C should not be an issue to the device's functionality.   You can double check on the power consumption on hardware vs powerplay analyzer to see if there is any anomaly on current drawn also.

[Altera_Forum]

"4.) When communicating with pll outputs and clock inputs on differential 3.3v what levels should I expect? 0V to 3.3V in phase and out? On one clock input I currently have -400mv to plus 3.6V and I can not find out why. the device feeding the signals in is set to 3.3V and bar a series DC blocking capacitor ( I know this generates negative volts ) I should still have 3.3V max! this may make my FPGA sick." 

 The overshoot of the signals due to reflection might lead to the 3.6V. This is generally due to impedance mismatch on the trace. You can double check on this by running IBIS model simulation to check the signal integrity.