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Board design with ep3c25q240 and ddr1 sdram

Altera_Forum
Honored Contributor II
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I'm trying to "Porting" cycloneIII starter kit with ep3c25q240 to avoid BGA package to cost down our product,but there's some problem on ddr interface usage if i want to use ddr controller IP 

 

to obey the pinout guideline easily,at first,i designed my Sch like this 

 

1.find ddr_dqs0 signal connected to U3 in cyclone III starter kit 

2.find U3 in cyclone iii pin information in f324 column. 

3.search the same raw,see which pin is in q240 column--it is 78 

4.assign 78 on ep3c25q240(in my sch design) as ddr_dqs0 signal. 

 

I tried to repeat 1-4 for ddr_dqs1, ok 

but when ddr_dm0, the raw which i found V3 in f324 column, do not have a pin number on q240 column. 

 

what's worse,i can find only to DM pin in Q240 column: 

80,dm5b 

232 dm5t 

but they are belongs to bank 3 and 8,so here is 2 problem 

1.I'm not sure whether DM signal could be at different bank 

2.since other ddr signal must be assign near them,i can't imagine how hard it will be when layout 

 

is there any suggestion? 

or is anybody controlled ddr1 sdram by ep3c25q240 successfully and can share me a Sch? 

 

thanks.
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Altera_Forum
Honored Contributor II
487 Views

The same problem, any suggestion? 

 

Thanks.
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Altera_Forum
Honored Contributor II
487 Views

ok , this is my solution, porting DQ and DQS pins to the bottom and top banks.  

 

mem_dm_from_the_altmemddr[1] Output PIN_232 

mem_dm_from_the_altmemddr[0] Output PIN_80 

mem_dq_to_and_from_the_altmemddr[15] Bidir PIN_231 

mem_dq_to_and_from_the_altmemddr[14] Bidir PIN_226 

mem_dq_to_and_from_the_altmemddr[13] Bidir PIN_221 

mem_dq_to_and_from_the_altmemddr[12] Bidir PIN_219 

mem_dq_to_and_from_the_altmemddr[11] Bidir PIN_217 

mem_dq_to_and_from_the_altmemddr[10] Bidir PIN_202 

mem_dq_to_and_from_the_altmemddr[9] Bidir PIN_201 

mem_dq_to_and_from_the_altmemddr[8] Bidir PIN_197 

mem_dq_to_and_from_the_altmemddr[7] Bidir PIN_81 

mem_dq_to_and_from_the_altmemddr[6] Bidir PIN_82 

mem_dq_to_and_from_the_altmemddr[5] Bidir PIN_87 

mem_dq_to_and_from_the_altmemddr[4] Bidir PIN_88 

mem_dq_to_and_from_the_altmemddr[3] Bidir PIN_93 

mem_dq_to_and_from_the_altmemddr[2] Bidir PIN_94 

mem_dq_to_and_from_the_altmemddr[1] Bidir PIN_98 

mem_dq_to_and_from_the_altmemddr[0] Bidir PIN_100
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