Bug: Dynamic PLL phase shifting breaks clock compensation

[Altera_Forum]

We have just finished producing some prototype cards based on the Arria V GX (5AGXMA3D4F27C5) and have a problem with the fPLL behaviour. 

 The setup is as follows: 1- An 125MHz input clock (N18+N19) feeds both a transceiver reference clock and the FRACTIONALPLL_X0_Y51. 2- The transceiver is set to use deterministic latency and tx_clkout feedback. 3- The fractional PLL is set to output 125MHz, 200MHz, and 25MHz clocks => VCO=1GHz. 4- The fPLL is set to direct compensation mode 5- We use the dynamic phase shifting feature of the fPLL to move the 200MHz and 25MHz clocks to align with a particular edge of the 125MHz clock  The problem we are having is that the 125MHz output clock of the fPLL has a different phase relationship to the transceiver TX clock on each power-on of the device. Since this card uses deterministic mode for synchronous ethernet, we need to transfer data from the fPLL 125MHz domain to the transceiver TX domain using a register-register. This is impossible when the phase relationship is different on each fPLL lock. The relationship is stable after power is applied, but the random 0,1,2,3,4,5,6,7 ns offset makes it unusable.  After further investigation with an oscilloscope: 1- every time the device powers on, there is a different multiple of 1ns between the TX clock phase and the fPLL output phase 2- comparing the external 125MHz signal to the transceiver shows the transceiver TX clock has the same phase relationship each time 3- comparing the external 125MHz signal to the fPLL's 125MHz output shows that it is the fPLL which has a different offset each time 4- Gutting the logic which shifts the 200MHZ/25MHz fPLL clocks (ie: feed the fPLL phase_en with '0') does not prevent the random phase offset  5- Changing fPLL compensation modes between direct, source sync, and normal does not prevent the random phase offset 6- Removing the dynamic phase adjustment ports from the fPLL instantiation *does* restore the phase relationship  So it seems to me that as soon as one enables the dynamic phase shifting feature of the fPLL, the PLL no longer correctly aligns the 125MHz output and input clocks. I would like to know if this is a bug in quartus or a bug in the Arria V GX.  For reference, the phase shifting feature is in demonstrated in http://www.altera.com/literature/an/an661.pdf, Figure 3.  Unfortunately, we need to be able to align the 200MHz clock for the use-case where this card will be deployed. Thus, I cannot disable the phase shift feature in production.   Has anyone else experienced / worked around this bug?

[Altera_Forum]

I've found the fix to this problem. The arria5 fPLL needs to be manually reset upon device power-up. The "auto-reset" in the megawizard doesn't do the job. Once I manually reset the fPLL, the clocks lined up like a charm.