Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Build HPS Hardware

Honored Contributor II

Hello, I have been searching for a guide that shows how to build the hardware for the HPS in Quartus. It would appear I use platform designer and create the necessary hdl from there, then add the .qip file to my project and set it as Top of Hierarchy. I have tried that and am getting these errors during place and route. 


Error (174068): Output buffer atom "hps_hps_0:hps_0|hps_hps_0_hps_io:hps_io|hps_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination  

I have provided my Platform Designer design in an image.  



Is there a guide for how to do this? Also, are there any special connections that need to be made in platform designer so I can open a terminal and interact with the Linux shell once I have built and booted the software? It seems every guide I check just talks about the hardware/software handoff and other software Linux tools that Altera offers, but I cannot find anywhere that demonstrates the basics of setting up the ARM in the hardware design. 


Xilinx has tons of User Guides for their Zynq PS and PetaLinux tools, so surely Altera must have them somewhere.
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Honored Contributor II

There is a tcl script to execute so that Quartus gets the correct pin assignments. I have no idea why this is not done automatically. 

Tools > Tcl Scripts. There navigate through your QSys project, synthesis > submodules folders, and there you should find a script whose name ends with pin_assignments.tcl . Select that script, run it and try and compile the project again