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CAM(Content Addressable Memory) into QDRII+ / DDR3

Altera_Forum
Honored Contributor II
‎05-12-2016 08:08 AM
1,680 Views

Hi, 

 

 

We need to implement a CAM using the QDRII+ / DDR3 memory. Basically a typical hash table implementation in FPGA.  

 

 

Altera provides example design for binary CAM. The implementation is based on M9K embedded memory. 

 

 

Is it possible to port the same CAM implementation into QDRII+/ DDR3 memory?  

 

 

Are there any latency statistics available? 

 

 

Thanks in Advance!
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Altera_Forum
Honored Contributor II
‎05-14-2016 06:44 AM
955 Views

What is the size of CAM that you need? 

 

The CAM design example uses an addressing method to implement a CAM, I do not think it is possible to do the same to DDRs. 

If you study the user guide, you will notice the big difference.
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