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vkc
Beginner
210 Views

CDR in automatic mode

Hii , i am using stratix 4 fpga in our design. I am using CDR in automatic mode. i followed the reset signalling according to the  manual. so rx_freqlocked and pll_locked is high but rx_plllocked is getting deasserted. But the manual tells that it should be either toggling or high and rx_signaldetect  is also always low.

i have tried loopback method it worked fine .But when i connected it to transmitter i am facing this issue. can anyone tell me what the problem might be.

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13 Replies
Deshi_Intel
Moderator
190 Views

CDR debug checklist

Deshi_Intel
Moderator
189 Views

HI,


I have attached CDR debug checklist in earlier post.


Although the debug checklist is for Cyclone 10 GX FPGA device but the concept of CDR debug is more or less the same.


You can review the checklist to get some clue in debugging your issue. I suspect highly related to either transceiver refclk huge PPM issue or your board signal integrity issue.


Thanks.


Regards,

dlim


vkc
Beginner
185 Views

Hii, my refclk is operating at 100MHZ, what is the idle ppm to be set during configuration.
Deshi_Intel
Moderator
168 Views

HI,


PPM setting is not related to clock frequency but rather depend on your on board crystal or clock generator chip performance.


Basically you want to relax the PPM setting by setting it to higher PPM setting like the max 1000 PPM setting if I am not mistaken.

  • Then as long as your on board crystal or clock generator chip PPM performance doesn't violate the 1000PPM limit, CDR should not loose lock


Thanks.


Regards,

dlim


vkc
Beginner
163 Views

hii sir,

The issue is with refclk. my pll input clk frequency from oscillator is 100MHZ, I am using altpll ip and i am deriving two clocks 50MHZ and 62.5 MHZ. But when i see it in signal tap the 50MHZ clock which is used for calibration is correct. But 62.5MHZ clock which is given for pll_inclk  and rx_cruclk is incorrect.

i am getting following warning  "clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by non dedicated input".

i am using stratix 4 fpga EP4SGX530NF4513N . quartus prime 14.0 tool and i have configured pin p23 as clock. find the pll configurations file attached below. please help me solve this.

Deshi_Intel
Moderator
156 Views

Hi,


As the warning explained, you are not using dedicated refclk pin to provide clock to CDR causing additional jitter that's impacting the clocking network performance.


To minimize jitter impact, you should be using dedicated refclk pin from the same transceiver bank as explained in below user guide doc table 2-2 Input Reference Clock Source (page 243)


Thanks.


Regards,

dlim


vkc
Beginner
136 Views

Hii,

The above issue got solved. I am facing synchronization issue.I am suppose to receive BC95B5B5 sync pattern. So I gave encoded pattern of BC95 in word alignment pattern(5F115) .I am receiving BC95XXXX at the data out and sync status signal is high. I tried the byte ordering pattern with 010110101.But it didnt help.. rx_signaldetect ,pll_locked signals are high. rx_plllocked is toggling.

I can also see the rx_errdetect and rx_disperr signal toggling. Please help me solve this.
Deshi_Intel
Moderator
128 Views

Hi,


If you sync status is high, that means you already achieved synchronization and likely this is bit error issue which correlate to 8b/10b decoder status error signal rx_errdetect and rx_disperr that are toggling.

  • The recommended approach to debug bit error is always to start to perform FPGA internal loopback testing to isolate whether this FPGA design issue or board design issue
  • If you have debug and pointed to likely your board design issue then one quick suggestion is to reduce your data rate speed to see if it helps


The other concern I have is what's your design rx_plllocked connected to ? pll loose lock is never a good sign and you should fix this issue first else functionality failure is expected as the PLL can't generate expected clock output in stable stage.

  • Are you using NativePHY or which IP that you are using ?


Thanks.


Regards,

dlim


vkc
Beginner
127 Views

I am using altgx ip.I have not connected rx_plllocked to anything in design.To what is rx_plllocked suppose to be connected.
Deshi_Intel
Moderator
122 Views

HI,


I checked the user guide doc (page 26)


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
59 Views

Hi,


It's been a while since I last heard from you


Did you manage to isolate whether this is potential FPGA design issue or your board issue via FPGA internal loopback debug test ?


Thanks.


Regards,

dlim


vkc
Beginner
57 Views

Hiii, I tried loop back method it worked fine.I recieved the correct data BC95B5B5. I tried decreasing data rate also I still face the same issue.

I am receiving data as BC95xxxx instead of BC95B5B5 when I connect it to a transmitter .my sync_status is high. Freq_locked and rx_plllocked behaving as per the hand book. Please help.me solve this.
Deshi_Intel
Moderator
52 Views

Hi,


I can only guide you to isolate issue but I can't help you to fix your board design or transmitter issue.


Since FPGA internal loopback design is working, you can then perform following to isolate whether it's board design or your transmitter issue

  • FPGA Tx -> board loopback via SFP loopback module -> FPGA Rx (don't use transmitter)


To isolate board design further, you can test out other Intel FPGA dev kit board if you have one


To isolate your transmitter issue, you can play around with transmitter PMA analog setting to see it helps out or check out other setting in your transmitter that may affect signal quality


Thanks.


Regards,

dlim