CEngine a new kind of embedded processor

[Altera_Forum]

The objective of this project is to provide a C platform for FPGA/ASIC applications with maximized performance. C source code is parsed and ram contents generated to be loaded into the chip's rams. A custom core then runs the application at speed that I think approaches an HDL design. 

 I only have a very basic test case and the program is not fully functional, so I need a way to decide if I should continue. I am not set up to run an NIOS simulation, so it would be a great help if someone would give me a realistic cycle count to run this case. If the cycle count is not significantly less than NIOS, THEN IT'S TIME TO FOLD MY TENT! Comparing to an HDL will be a lot tougher, I think.   The controls are not complete, but the slack at 100Mhz is estimated at about 7. 5 ALUTS , and 5% or so of memory for an EP3SL50 Stratix III The memory is not full because it has capacity for a couple of k each of C statements, variables (32 bit), expressions.   The test case takes 51 clock cycles, 36 of which are the 9 iterations of the for loop.  The program still needs work, but I am uploading a zipped .exe for tryout. To try it, you will have to get past your security, but at least you won't have to do a complete install. It should start with an open file dialog where you can select the testcase attached here to try first, then do some editing of the testcase if you want. It is not fully tested, so I can't promise too much.