Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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CIII Configuration Schemes

Altera_Forum
Honored Contributor II
‎02-20-2009 06:42 PM
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Hello, 

 

I have a CIII and an EPCS4 device. I currently use the SFL configuration scheme, meaning that I download a new image via JTAG/ByteBlaster and allow the FPGA take care of the AS programming to the config device. 

 

My question is can I tie a microprocessor onto the JTAG bus and configure the EPCS4 with a new image? If so, would my micro just take the .jic file and push it into the FPGA, as the ByteBlaster does now? Where can I find the JTAG commands and sequence needed to do this? 

 

Thank you much, 

Rob
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Altera_Forum
Honored Contributor II
‎02-20-2009 11:07 PM
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It's certainly possible, but most likely undocumented as a whole. You'll find detail documentation of several protocol parts involved with this action. If you are designing a new FPGA board, I suggest to connect the AS memory directly to the processor intended to perform programming. There are also Altera software examples for embedded AS programming, I think.

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