CONF_Done, nStatus not fully released (expected 3.3V, is 2V)

[Agdepusen]

Hi,

this is probably my 20th Altera board, but this error puzzles me.

It's a modification to an existing design which works fine.

Power cycling is good.

All supplies is present and stable

JTAG signals looks good. 10k PU.

But absolutely no activity on TDO when I start the JTAG session.

Further, CONF_Done, nStatus is not fully released (expected 3.3V, is 2V).

Any ideas out there?

Programming voltage is 3.3V and is verified.

Device is Cyclone V, A7, 486 pins.

[AnandRaj_S_Intel]

Hi,

1. Does the nSTATUS signal low from the beginning right after power up? Or during in the middle of configuration process, the nSTATUS from high (logic 1) then suddenly goes low (logic 0)?

• If the nSTATUS is low from the beginning right after power up, then even JTAG configuration with .sof file would failed. 
• If the nSTATUS from high (logic 1) then suddenly goes low (logic 0) during middle configuration process, then either due bitstream corruption or power issue.

2.Have programmed .sof file via JTAG configuration ?

If the .sof file can be configure via JTAG successfully then the LED should blink. Thus it is not a power issue since JTAG configuration is successful. If the JTAG configuration with .sof file failed, thus it is a power issue. 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

[Agdepusen]

After power up it partially releases the nStatus to 2.0V. And no joy with JTAG.

We suspect solder or chip error. Most likely solder since we have two identical boards with same error.

We have manually compared the successful layout with the new one, and they do not differ.

[Agdepusen]

False alarm.

PCB production error. VCCPGM only did get supply on 2 out of 3 pins. Apparently these pins are not internally connected.

Thanks, you may close this request