CPLD CLock divider?

[Altera_Forum]

I have been a long time MAX user. In the old days when I needed to divide a clock I would just use the counter output to drive the clock input of my destination flip flop. This always worked well in MAX products.  

 When I transitioned my designs to MAXII I continued to do the same thing. The problem I ran into was that I was using all the global routes for other control signals. This prevented my divided clock from getting on a global. The result was I could not meet timing since my divided clock fed a lot of flip-flops. When I used a clock enable all my problems went away.  My question: Is it always better to use a clock enable versus a divided clock? Is there a situation where a divided clock is better than an enable?  I never worried about this in traditional CPLDs but with these new devices it is something to consider.

[Altera_Forum]

There are timing reasons that make it always better to use a clock enable instead of a divided clock. However, it might be a lot of trouble to change existing source files to use the clock enable for many destinations, and the paths driven by the clock enable will have to run in a single clock cycle. My post at "Altera Forums > Tools Related > Quartus II Discussion > PLL Clock Frequency" describes a case where it is OK to use a divided clock.