Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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CPLD Configuration Architecture


In CPLDs, is there a difference between Configuration Memory and Program Memory? I understand that FPGAs load data from a non-volatile source into the LUTs, and I'm wondering if CPLDs do something similar. In other words, if I read back the configuration memory of a MaxV CPLD via the JTAG interface, are the returned bits the exact programmed values or is it possible that the program memory is different? I know that in FPGAs they can be different (SEUs) and am trying to find out if it's the same for CPLDs.

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Hi RHark,


Configuration Memory and Program Memory are similar. Some people called it Configuration memory and some called it Program memory.


When you read back the configuration memory of a MAX V CPLD, it returned the exact programmed values bits but the orientation of bits might be different from the programming file. This bit differences due to Little/Big Endian or LSB/MSB.


I hope this help.


Thanks. 😉

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