CPLD Newbie

[Altera_Forum]

Hi, 

 An older EE here who has NEVER done anything with CPLDs. I know nothing! :)   Is there a good book or somewhere on the web that shows where to start?   I have a very basic circuit that I would like to implement with a CPLD.   I am interested in using something with a very high speed/slew rate & lowest propogation delay.  It looks like FPGAs might be better in this area than CPLDs? But the FPGAs seem more complex?  Thanks

[Altera_Forum]

--- Quote Start ---  Hi,  An older EE here who has NEVER done anything with CPLDs. I know nothing! :)   Is there a good book or somewhere on the web that shows where to start?    --- Quote End ---    I would start by looking at learning some basic Verilog or VHDL. (Depending on your companies preference) http://www.sutherland-hdl.com/ offers training on this front. But they also have some verilog language reference manuals etc. Although some of the tools still exists the days of entering schematics to capture the design are really over. Once you have a good simulator, and Verilog under your belt, the sky is the limit.    --- Quote Start ---  Hi, I have a very basic circuit that I would like to implement with a CPLD.   I am interested in using something with a very high speed/slew rate & lowest propogation delay.  It looks like FPGAs might be better in this area than CPLDs? But the FPGAs seem more complex?   --- Quote End ---    For the best performance, IO Slew rate, and propagation delay an FPGA will be faster, however they will also cost much more. because they are capable of much larger designs.  Since the design is very basic, the CPLD is probably your best bet unless the design just doesn't meet your performance requirement. I would look at the MAX V family, then compare it to the smallest Cyclone IV family member. You'll see the difference in size and performance pretty quickly. Cyclone V is really nice and much faster than Cyclone IV, but the smallest member is not out yet, and most likely overkill for you.  The nice thing is once you have the Verilog source, you can target different CPLD's/FPGA's and see how fast the design will run in different families. This will also let you know how "Big" is your design, so you can target the correct device before laying out the board.    Pete