CPLD clock issue

[Altera_Forum]

This might be a stupid question but I need to see where is the problem. 

 I have two designs with an Altera CPLD MAX3000A, the difference between them is the clock input signal. Both clock signals have 13Khz frequency and 5V input signal.  - The first design clock input comes from an 4106 Schmitt trigger and has 50ns raising and falling time. - The second design clock input is from a Schmitt trigger made with an amplifier configuration and has 1us raising and falling time, given by amplifier's slew rate.  The second design (the one with clock slew rate 5V/us) shows almost at all times a randomly erratic behavior and I guess this is happening because of a much larger clock raising time. Is this true? Is it anything I can do to make the second design work with the clock that I have?

[Altera_Forum]

MAX3000A has a maximum rise/fall time specification of 40 ns for inputs. Without an external schmitt-trigger you won't get clean edges, that can drive edge sensitive design parts without errors.

[Altera_Forum]

Thanks FvM, it's pretty clear for me now where things go wrong, but I still have one more question. 

Is is possible to use that high rise/fall time signal as an input, clean the edges inside of CPLD and then use it as a main clock signal?