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It appears to be so. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide shows the CVP data path to be from PCIE to the SDM and then to the core logic of the FPGA.
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It appears to be so. Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide shows the CVP data path to be from PCIE to the SDM and then to the core logic of the FPGA.

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