Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,107 Views

CVP on Arria 10

Hi, 

I have been trying to use CVP on Arria 10. This is hosted on a Ubuntu Host. I am using stock altera_cvp drivers. 

The core programs correctly and the drivers report success after the .rbf copy. The driver unloads with no problem. 

 

However, the design does not function after programming. I read back 0xffffffff from all bars. i do not see any tlps on the rx bus of the hip when accessing the bars. This suggests that the HIP is not forwarding the read/write TLPs. 

lscpci reports look good but I noticed bars are disabled after CVP. This is not a problem as our application module appears to re-enable them successfully. 

 

If I do a warm restart, then the design functions correctly. It also functions correctly if we do a non CVP build so it is known good.  

So, immediately after CVP reconfig no TLPs from HIP. After a host warm restart TLPs all good! 

 

I assumed an issue with the resets but have tried a few things with no success. 

Has any one else seen such a thing? 

 

Many thanks 

Vern
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
126 Views

Hi, 

I observed similar behaviour with Arria 10 GX PCIe card (Attila Instant-DevKit). When using altera_cvp driver, the FPGA configuration with .rbf file succeeds. 

But BAR access doesn't work, I also read 0xffffffff values instead of some known register bits. After warm restart the BAR access finally works. 

A warm restart is not needed if I remove the PCIe device first (e.g. via sysfs by "echo 1 > /sys/bus/pci/devices/0000\:42\:00.0/remove") and then do a bus 

rescan (e.g by "echo 1 > /sys/bus/pci/rescan"). 

 

Any clue how to debug this? Or did you already find a solution? 

 

Here, some infos from lspci. Before CvP configuration: 

$ lspci -d 0x1172:0xe003 -vv 

42:00.0 Unassigned class [ff00]: Altera Corporation Device e003 (rev 01) 

Subsystem: Device 4e1b:4e0c 

Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 

Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 

Latency: 0, Cache Line Size: 64 bytes 

Interrupt: pin A routed to IRQ 31 

Region 0: Memory at f8300000 (64-bit, prefetchable)  

Region 4: Memory at f8000000 (32-bit, non-prefetchable)  

Capabilities: <access denied> 

Kernel driver in use: Altera CvP 

 

After CvP configuration (BAR access not working): 

$ lspci -d 0x1172:0xe003 -vv 

42:00.0 Unassigned class [ff00]: Altera Corporation Device e003 (rev 01) 

Subsystem: Device 4e1b:4e0c 

Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 

Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 

Interrupt: pin A routed to IRQ 31 

Region 0: Memory at f8300000 (64-bit, prefetchable) [disabled]  

Region 4: [virtual] Memory at f8000000 (32-bit, non-prefetchable)  

Capabilities: <access denied> 

Kernel driver in use: Altera CvP 

 

After PCIe device removal and bus rescan (BAR access working): 

$ lspci -d 0x1172:0xe003 -vv 

42:00.0 Unassigned class [ff00]: Altera Corporation Device e003 (rev 01) 

Subsystem: Device 4e1b:4e0c 

Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 

Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 

Interrupt: pin A routed to IRQ 31 

Region 0: Memory at f8300000 (64-bit, prefetchable)  

Region 4: Memory at f8000000 (32-bit, non-prefetchable)  

Capabilities: <access denied> 

Kernel driver in use: Altera CvP 

 

Thanks, 

agust
126 Views

Hi Vern

you can find the memory space and bus master enable were cleared

Control: I/O- Mem- BusMaster- .......

so you need to enable enable them .

  1. if the memory space (Mem+/-) enable is not set , then all the memory read and memory write target the BARs of this Endpoint will be treated as unsupported request, and the PCIe root port will map this CPI(UR status) to all F data transaction
  2. if the bus master enable is not set , the endpoint can't issue the memory read and memory write upstream , such as the host, all these transactions will be blocked within the PCIe endpoint

so , you can enable them by the setpci command since you are working at Linux OS, before that you need to know the bus:dev.func number , you can use the "lspci -vt" to list the PCIe tree, assuming the bus:dev.func in your system is 02:00.0

setpci -v -s 02:00.0 COMMAND.B=0x6

Then you can perform the lspci -vvvs again to check whether the memory space and bus master enable are set correctly

 

PSG support team​

Reply