I have been trying to make CVP on Cyclone V 5CGTFD7C5U19C7 FPGA. My requirement is Gen2 Lane2 PCIE interface with CVP enabled. My FPGA board has Gen2 Lane2(X2) M.2 interface.
I downloaded altera PCIE example projects (Gen 2 X1 and X4 examples) and created and configured Gen 2 X2 project based on X4 project. I successfully tested all X1, X2 and X4 examples without CVP(Although my FPGA board supports only X2, I beleive altera X4 PCIE automatically downgraded to X2)
Then I enabled CVP, and only X1 example was working properly.
In all 3 cases, peripheral image seems to be loaded properly into FPGA. CONF_DONE pin goes high and CVP_DONE pin stays low immediately after power up. In X1 project, device is shown as PCIE device in device manager and CVP_DONE goes high after loading .rbf image. But in X2, and X4 projects, PC doesn't recognize the device's PCIE interface. I believe this issue is related to splitting logic into core and peripheral images.
I have successfully tested CVP with X4 in Cyclone V 5CGTFD5C5F27C7 and 5CGTFD7D5F27C7 devices. Is it possible to have any limitations related to CVP in U19 package?
Any suggestion to investigate this CVP issue is highly appreciated.
I guess this is a known issue that x2 does not work in CVP. The following is from Intel KB on CvP:
Known Issues and Solutions