CYCLONE III POR AND DEV_CLRn TIMING CONSTRAINT

[Altera_Forum]

Hi, i have a Cyclone III configured in AS mode start-up and a supervisor circuit that drive the DEv_CLRn input pin. The supervisor circuit have a fixed delay time to switch its output from low to high. i'm wondering if there are timing constraint between the load time from the EPCS memory and the time at which the DEV_CLRn pin go high.

[Altera_Forum]

I may not be understanding your question right but there is no 'constraint' required between any point during configuration and a change to DEV_CLRn. 

 Toggling DEV_CLRn during configuration won't have any effect on register states or the configuration process. Toggling it once the FPGA is configured will cause the FPGA to behave as stated in the 'Optional Configuration Pins' (Table 9-23 in the configuration, design security, and remote system upgrades in the cyclone iii device family (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyc3/cyc3_ciii51016.pdf)). So, assuming you've enabled the device wide reset (within your project) it will clear the registers.  The 'Configuration Requirement' section from the same document (page 9-5) discusses the POR times for various configuration schemes. Also see the 'Estimating AS Configuration Time' section on page 9-20. This discusses the configuration times you can expect in AS mode.  Cheers, Alex