CYCLONE IV E : Connect FF to PLL_OUT pin as differential I/O

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

CYCLONE IV E : Connect FF to PLL_OUT pin as differential I/O

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I was thinking that connect user logic to PLL_OUT pin as differential I/O. But an error occurred by fitter(Place & Route).

Error ID : 176150

Error Message : Pin "<name>" with RSDS_E_1R I/O standard must be driven by the external clock output of an enhanced PLL

I seem to be able to connect FF to PLL_OUT pin as differential I/O on Chip Planner.How can I avoid this error?

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