Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20688 Discussions

Calculating jitter

Altera_Forum
Honored Contributor II
1,273 Views

I see a PLL output jitter spec of 25mUI for clocks less than 100MHz. Does anyone know how to calculate the output jitter with this spec?

0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
483 Views

25x10ˆ-3 (10ns) = 250ps 

 

Where 10ns is the period of the clock you are using.
0 Kudos
Altera_Forum
Honored Contributor II
483 Views

UI is unit interval, which is the period of your clock in this case. mUI is 0.001UI. Based on that you can calculate your jitter for whatever period clock you have.

0 Kudos
Reply