Can CPU win arbitration during DMA operation to the same data bus?

[Altera_Forum]

Hi all 

 I am using the SOPC builder for my NIOS II system design.  I am having the 1Mx16 SSRAM and the 4Gb Nand Flash both sitting on the same data bus. The SSRAM is for NIOS II cpu instruction and data. The Nand Flash is for storage of the acquistion data. Form time to time, I will be doing a DMA to burst 2K byte of data from the Nand Flash to an external IO port.   My question is: Can I do this without real time consequence.   While the DMA is in the middle of pulling 2K data from the flash, if the CPU also need to do read/write to the SSRAM, how will it impact the performance. Will the CPU need to wait all 2K of data pulled out before it can touch the SSRAM again. Or the CPU will win the arbitration and touch the SSRAM first before the DMA finish (such that the performance impact is minimize)?  Thanks Steve Chan

[Altera_Forum]

Edit: I misread you, as if you were DMAing from the flash to the SSRAM. 

The Qsys fabric Master1 access Slave1 while Master2 accesses Slave2 without contention.  What I wrote below only applies when two or more masters try to access the same slave.  ------------------ The CPU will given access.  The arbitration scheme uses a fairness scheme. By default, it gives each master one access, round robin. If needed, you can change the weights in Qsys.  Check Qsys interconnect handbook, 7-10.