Hi,I am using Cyclone V. And right now there is 100MHz differential clock to connect to REFCLK in the transceiver part as clock source. Here I am just wondering whether this 100MHz REFCLK to be used as clock resource for other bank's IO pins. Thanks,
The Cyclone V transceiver handbook shows the dedicated REFCLK input being fed onto the internal clock network implying (in my view) it can. However, it doesn't seem to be more specific as to whether that can then be used for clocking other registers or IO.I suggest you let Quartus tell you. Put together a simple design or add a clocked output signal to your design driven from the transceiver's REFCLK. Then run it through Quartus. It'll give you a simple yes or no. Cheers, Alex
By default, the CV transceiver refclk cannot be use to drive core user logic or general purpose IO. However, you can workaround by having transceiver PHY clocked by the refclk and then tap the refclk signal to core. Without the transceiver PHY in place, the design could not pass Fitter.
Sorry to reply to such an old thread, but I have a similar question. We're using a Cyclone V and the only available clock input is a "Dedicated Transceiver REFCLK". I am feeding that into a PLL (altera_pll megafunction) that is used to clock FPGA fabric. We're not using any transceivers.It compiles fine, so the tools seem ok with it. I set the IO Standard to LVDS. I found this that also seems to say it is ok: https://www.alteraforum.com/forum/attachment.php?attachmentid=14119 But some knowledgeable people here seemed to question it. I did not do anything special with workarounds. But we're about to get a board made and it would be nice to have a clock. Can someone confirm that this is ok.
This is the sort of question Quartus will answer for you. Put a small, clocked design together. Constrain it so that the logic is clocked from the pin you're feeding the clock into and run it through Quartus. If it's possible Quartus will fit the design. If not, it won't.Cheers, Alex