If I use a PCIe IP with Qsys,and use DMA mode to transfer video data to our ARM SOC.Can DMA IP use a different clock compard with PCIe IP? If so,When I write,for example,512 bytes to PCIe Tx, and the DMA uses a lower clock, How does PCIe IP know when the writing transfer is end? OK,from another view,when does PCIe IP know when the DMA writing operation is end has nothing to do with the DMA's clock.
use dual clock FIFO between DMA-IP annd PCIe-IP.the FIFO solve timing problem unless receiver's data rate is slower than sender's. the other question. when PCIe-IP know the DMA is done? there should be interrupt signal. when interrupt becomes high, your BUS-Master ( ARM in this case ) knows it is done.
Thanks akira.And for the first question, for PCIe transmit,the sender has to use a same clock with PCIe. For the second quesion. In DMA write mode, ARM SOC order DMA IP to transmit to write data to its(ARM) RAM. And then DMA start to operate,when transfer is done, DMA can send a IRQ through PCIe. ARM knows that it is done . BUT,in this case,How does the PCIe IP know the transfer is done? The IRQ is just sent through PCIe IRQ channel.The PCIe doesn't know the meaning of IRQ. And accroding to the PCIe protocal,there are data length in TLP,how does PCIe IP knows the payload length?
> And for the first question,> for PCIe transmit,the sender has to use a same clock with PCIe. sorry I don't get it > ARM knows that it is done. > BUT,in this case,How does the PCIe IP know the transfer is done? >The IRQ is just sent through PCIe IRQ channel.The PCIe doesn't know the meaning of IRQ. of cause not. PCIe is a bus protcol. how shoud IP-core know the dma done? bus IP-core just transfer information between busmasters and slaves. interrupt is just information of its status. > And accroding to the PCIe protocal,there are data length in TLP,how does PCIe IP knows the payload length? I don't know which IP-core you use. but there must have the setting for payload size. payloadsize is fixed before you compile FPGA. and knowing payload size is not your job.( setting it is yours ) are you creating PCIe-IP core on you own? if so, I'm sorry forget about all my advice. do you still have question?
And it seems that I understand.In the PCIe IP spec, the part which describe the interface of PCIe IP help me understand the details of Avalon-MM transferring. Combining your reply and the PCIe IP spec,I think I understood. I use the altera hard PCIe IP. Thank you very much.akira.