Can DMA perform this application?

[Altera_Forum]

Hi, 

 My application requires the following functionality with which I can get huge speedup. I want to read the data from sdram 4 bytes at a time, perform some computations and write back to sdram at a different location. This is being implemented in software and so nios processor is taking lot of time to read, do computations and write back. So, I am planning to implement HW for the computations and use DMA for transfers to it. I dont want to implement any additional storage logic to store the computed values inside the HW. So, to use DMA I have to ensure that I read the values using DMA and write the computed values using DMA to SDRAM in alternate cycles, i.e., 1 read and 1 write. The computational block will be combinational logic and will be done in the same cycle. Is there a way to do this?  Thanks, Gangi.

[Altera_Forum]

You can use two DMAs and add your own logic between them, but you will need a kind of FIFO buffer. There is no way to know in advance how many wait cycles your DMAs will have when attempting to read or write, so you can never assume that you'll have a write one cycle after each read.

[Altera_Forum]

You can also wedge your logic in between the read and write master of this DMA: http://www.altera.com/support/examples/nios2/exm-modular-scatter-gather-dma.html 

 Since it's all based on standard Avalon interfaces anything with ST interfaces can be placed in between the masters. I found it to be pretty easy to throw other things in between like filters, byte flippers, etc.... Just remember that Avalon-ST uses big endian symbol ordering so the byte read from offset 0 ends up being stuffed into the upper bits of the ST data. If you prefer to work on the data using little endian just flip the symbols (bytes) coming into your widget, crunch the data, flip the symbols back around before passing the data to the write master. These byte flips are just wires so they come for free.

[Altera_Forum]

Hi,  

I have a question concerning the GO bit of a DMA controller core.   Can the GO bit be used to pause a DMA transfer? In other words, by changing the GO bit from 1 to 0, will the current DMA bus cycle complete and release the bus so that some thing else can access the destination memory for example, and reset the GO bit to 1 to resume the DMA transfer?

[Altera_Forum]

Here is the 'go' bit behavior amongst the various DMAs: 

 DMA --> Writing '0' to the go bit will not stop the DMA SGDMA --> Writing to the stop bit in the control/status registers will stop the SGDMA on a descriptor basis (I think.... it's been a while since I've used it) Modular SGDMA --> Writing the to stop bit will allow the bus transfer to complete and then it will stop. Dito if you reset it.

[Altera_Forum]

Thanks for you help!