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Valued Contributor III
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Can I expect PLL outputs to be in phase?

If I implement an ALTPLL in a cyclon V with an input clock of 26 MHz and 2 output clocks (one at 26 MHz and one at 4x 26 MHz = 104 MHz). Can I expect the two output clocks to be in phase? 

 

 

If so, is it ok to have a "set_clock_groups -asynchronous -group [clockA] -group [clock B]" sdc command to ignore timing between these clock domains and then just cross between these 2 clock domains as needed without problems? Or is that constraint not even needed because the tool would know that the 2 clocks are actually synchronous? 

 

 

I have read the documentation about the different pll modes (direct, normal, etc.) but don't completely understand if a certain mode would affect the phase relationship between the 2 output clocks. 

 

 

Thanks for your help!
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Valued Contributor III
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The output clocks are in phase and synchronous. You don't need the set_clock_groups exception unless you specifically do not want timing analysis performed on transfers between the two clock domains.

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Valued Contributor III
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--- Quote Start ---  

The output clocks are in phase and synchronous. You don't need the set_clock_groups exception unless you specifically do not want timing analysis performed on transfers between the two clock domains. 

--- Quote End ---  

 

 

Thanks for the quick reply. Is this the case for any PLL mode (direct, normal, etc.) or just for a certain mode?
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