Can I transmit and receive SRIO packets only with Avalon ST Interface?

[SYiwe]

Hi, everyone

I instantiate a RapidIO IP Core and the transceivers are connected to CPS1848(RapidIO Switch), here's my questions:

(1) Can I transmit and receive SRIO packets only with Avalon ST Interface, instead of using Avalon-MM?

(2) I assert the revelent signals(gen_tx_*) according to RapidIO IP core user guide, but I cannot find the value of ftype and ttype of SWRITE transaction in the user guide, where can I find the definitionof ftype and ttype?

(3) I found a reference design in AN836, but I can't download the example design(srio2_s10_avst_6g_de.par) because the website cannnot be accessed, is there any way that can download the design? Here's the link in AN836: http://fpgacloud.intel.com/devstore/platform/17.1.0/Pro/stratix-10-rapidio-ii-avalon-st-pass-through-interface/

Thanks, regards.

[Nathan_R_Intel]

Hie, Please check my replies to all your questions. (1) Can I transmit and receive SRIO packets only with Avalon ST Interface, instead of using Avalon-MM? No, you cannot with the current RapidIO IP Core. The logical layers interface is using Avalon-MM. (2) I assert the revelent signals(gen_tx_*) according to RapidIO IP core user guide, but I cannot find the value of ftype and ttype of SWRITE transaction in the user guide, where can I find the definitionof ftype and ttype? You can refer to the following document on Transcation ID details for ftype and ttype. Refer to section 4.4.2 and Table 28. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug_rapidio-17-0.pdf Regards, Nathan