Can an external pull up on an open drain pin go to a voltage greater than VCCIO?

[Altera_Forum]

Can an open drain pin be pulled up externally to a voltage greater than VCCIO (but less than the absolute max...)? 

My Cyclone III INIT_DONE is on a 1.8V bank but I need to interface with a 3.3V LVCMOS processor pin. I need to get the output to > 2.0 V to meet the processor's VIH[SUB]MIN[/SUB]. It would be cute if an external pull up to 3.3 would work, but I'm concerned that I'll be turning on some parasitic diode or the top FET in the output driver.  If it can be done, please direct me to a reference in the datasheet or handbook that sanctions it.

[Altera_Forum]

I found an indirect answer on their answer database 

http://www.altera.com/support/kdb/solutions/rd06292008_741.html  It basically stated that it will work as long as they are below absolute max Vin.  But this was for Stratix III.  Pete

[Altera_Forum]

Thanks Pete. The associated threadery reinforced your inference. You'd think they'd be a little more plain about it in the datasheets, though. 

Tweet

[Altera_Forum]

I agree. I looked through the handbook, and couldn't find any reference that stated if it was ok to pull it above the VCCIO of the bank in open drain mode.. 

 Pete

[Altera_Forum]

At final you can try to add a voltage divider with 3 resistors such as getting no more than 1.8V at the "upper end" of the lower resistor connected between FPGA CONF_DONE and ground but more than the required 2V the upper resistor connected between 3.3V and the µC. The third resistor being installed between these two connect FPGA and µC, also providing the voltage drop to bridge. Maybe tricky to scale this to ensure high and low levels are within the limits required by the FPGA and µC but both pins are high ohmic, thus this might be worth thinking about...

[Altera_Forum]

based on conventional knowledge if you have common ground and use open drain in saturated state (letting current to flow through it) and having an external resistor; -it will drop let's say 3.3volts across a resistor even if your fpga bank vccio is 1.8 or something else. so your uC will see that branch with resistor as 3.3v . this is as far as my knowledge gets me so be careful there might be some other considerations to take in count. 

 but i fear you mess things up a little bit. INIT_DONE is a 2 CMOS pin.fpga's pullup transistor is saturated when pin delivers current, and it's lower transistor is saturated when pin sinks current. (https://www.altera.com/en_us/pdfs/literature/hb/cyc3/cyc3_ciii51007.pdf page 11) now imagine if you hook up INIT_DONE to the open drain COMS output: when from fpga a "1" will enter into your open drain transistor gate, it will saturate and sink current that is present on the pin; your external resistor will drop 3.3volts across it. but what will happen if fpga sends 0 to transistor's gate? it will become high Z. and the pin will basically disconnect itself from circuit. so your resistor will never have a "0" state. that uC on the other end will see either 3.3v or high impedance. but never 0. i can't imagine how is it possible to use an IO signal with open drain configuration.  from what i can imagine in order to achieve the goal in your way, with open drain, only solution seems to be is to connect 1 more resistor parallel to that fpga pin. and another end to vcc. like two resistors, one will come from your uC and another from vcc. when Open Drain is saturated, all the currents from uC and vcc will sink into the fpga pin. across the external resistors of cource. and your uC resistor will have 3.3v drop across it. but when fpga Open drain cloases and cuts itself off the circuit; only circuit that can supply current to your uC will be that vcc resistor. it's called pull up resistor configuration. so your uC pin will not see high impedance it will see 3.3 input. and uC external resistor will have some voltage drop but in opposing direction. ...i guess......... ...hmmm. am i missing something?