Can conditional builds be performed in VHDL?

[Altera_Forum]

I'm relatively new to VHDL and am looking for a way to perform conditional builds. I'm aware of the `ifdef that is available in Verilog, but am trying to find a comperable method in VHDL.

[Altera_Forum]

Depending on what you are doing perhaps the "generate" statement can help.

[Altera_Forum]

I think a combination of generic parameters and the generate statement should do the job.

[Altera_Forum]

I just tried a test case using the generate statement and generic parameter. That 

looks like it will do what I need. Thanks for the tip.

[Altera_Forum]

Hi wolson, 

 As I am a quite lazy, each time I have a repetitive structure to implement, I use the FOR-GENERATE statement (I am rather keen on coding with AHDL instead of VHDL but it's very similar). That works well nevertheless when it comes to use the PARAMETER statement (to parameterize a port size for instance), I do have some trouble to pass the parameters down along the project hierarchy (from the top-level entity to lower level entities).  The "parameter value search order " section given in the Qts II help is a bit confusing so I was wondering whether you experienced a similar problem (I'm often use the PARAMETER statement in BDFs) ? ...  Thanks.   Oliver

[Altera_Forum]

Oliver: 

 I'm not familiar with AHDL, but I suspect that the "PARAMETER" statement you refer to is the same as VHDL's "generic". I've used that before, but for parameterizing between two levels only. I suspect that there would need to be a precedence rule when passing a parameter between multiple levels.  In the case of my recent experiment with generic/generate, I used that to cut down on editing between simulation vs. system build versions. The previous engineer for this project would comment out and uncomment portions of code each time. I modified the lower level entity with a generic to default as a simulation version by generating it's own signals normally passed in on input ports from the higher level entity. The higher level entity that instantiates the lower overrides the lower level entities’ generic default by passing in a value to use the system build version of code.