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CBlow
Partner
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Can the TSE MAC driver access register 16?

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hello,

 

While trying to resolve what is believed to be a PHY‑related issue,  my customer has been doing a fair amount of digging through Tri‑Speed Ethernet MAC driver code.

----- extracted from QP_v18dot0_DMR_Ethernet_bsp\drivers\inc\altera_avalon_tse.h -----

/* PHY register definition */

enum {

    TSE_PHY_MDIO_CONTROL    = 0,

    TSE_PHY_MDIO_STATUS     = 1,

    TSE_PHY_MDIO_PHY_ID1    = 2,

    TSE_PHY_MDIO_PHY_ID2    = 3,

    TSE_PHY_MDIO_ADV        = 4,

    TSE_PHY_MDIO_REMADV     = 5,

 

    TSE_PHY_MDIO_AN_EXT             = 6,

    TSE_PHY_MDIO_1000BASE_T_CTRL    = 9,

    TSE_PHY_MDIO_1000BASE_T_STATUS  = 10,

    TSE_PHY_MDIO_EXT_STATUS         = 15

};

 

PHY transmitter control resides in page 0, register 16 (i.e., Copper Specific Control Register 1).  We haven’t found any references to this register in the TSE driver code, and the enumeration above ending at 15 suggests that it won’t.

Alaska

8831510/881518/

88E1512/88E1514

Doc. No. MV-S107146-00 Rev B

Pages 117 – 119

Table 89:  Copper Specific Control Register 1

Page 0, Register 16

 

The PHY register definitions in altera_avalon_tse.h suggest that page 0 registers 0 through 15 are standard across all PHYs, we're hoping that extends to register 16.

Can anyone confirmation that the TSE driver doesn’t touch this register?

 

thanks in advance.

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Accepted Solutions
Deshi_Intel
Moderator
100 Views

Hi CBlow,

From TSE MAC side, it does support MDIO reg mapping till 32 reg as shown from below TSE user guide doc.

So, I think  you can advise your customer to modify the driver design to fit to customer board external PHY chip reg mapping.

Thanks. 

TSE MDIO map till 32 reg space.png

Regards,

dlim 

View solution in original post

1 Reply
Deshi_Intel
Moderator
101 Views

Hi CBlow,

From TSE MAC side, it does support MDIO reg mapping till 32 reg as shown from below TSE user guide doc.

So, I think  you can advise your customer to modify the driver design to fit to customer board external PHY chip reg mapping.

Thanks. 

TSE MDIO map till 32 reg space.png

Regards,

dlim 

View solution in original post