Cannot connect PLL to internal signal in Cyclone IV

[Altera_Forum]

Hello Everyone, 

I am trying to place a PLL macro after a frequency synthesizer in a Cyclone IV FPGA and it looks like this is not possible. As a workaround I had to route the synthesizer output to a I/O pin, create a jumper on the PCB and then brought it back to the FPGA through another I/O pin and only like this I could route it to a PLL macro. My circuit works well like this but I was wondering if anyone knows of a way to connect the PLL macro directly to the internal signal of the frequency synthesizer without going out of the FPGA and back in.  Regards, Cosmin

[Altera_Forum]

What is the "frequency synthesizer"? A programmable divider implemented in LEs? That's in fact not supported. Cascading PLLs is basically possible, but logic generated clocks as PLL input isn't.

[Altera_Forum]

Hi FvM, thank you for the reply. Yes, my synthesizer uses logic generated clocks. So I understand that it is not possible to route the output of my synthesizer to a PLL input. I am trying to port a design from Xilinx FPGAs to Altera/Intel, and Cyclone IV was my first try. All Xilinx FPGAs that I've tried so far (Spartan 3, 3A, 3E, 6, and Zynq) allow me to connect the logic generated synthesizer output clock to a PLL so I am surprised to learn that Cyclone IV does not allow this connection.  

 Is this limitation only for Cyclone IV or for all Altera/Intel FPGAs?   Regards, Cosmin