Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20754 Discussions

Cannot obtain error free IBIS model to do DDR4 sim in Hyperlynx.

scavis
Beginner
490 Views

Every time I generate an IBIS file from the 10AX027H3F34E2SG it seems to be missing some signals. For me to proceed it would be very helpful if I could download somewhere a pre-generated aria10 IBIS file with . With that file I could do the bring up of the Hyperlynx testbench. Next step would be to figure out what is going wrong with the IBIS model generation.

I have a similar issue when generating the IBIS file from the Terasic reference design (DDR4 project). https://www.terasic.com.tw/cgi-bin/page/archive.pl?anguage=English&CategoryNo=228&No=1108

0 Kudos
0 Replies
Reply