Cascaded clock control blocks?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Cascaded clock control blocks?

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I have a high fanout clock (CLKA) that I would also like to feed into a clock mux (CLKB). When I instantiate two clock control blocks for this purpose the fitter complains that the outclk port of the first (CLKA) can't drive the inclk port of the second (CLKB). Is what I am attempting even possible?

Thanks,

Raphael

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