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Valued Contributor III
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Change Bar's size in PCIe Simulation

Hi guys!!:) 

Well, I'm trying to simulate a PCIe communication and I have the next trouble. 

 

 

I'm using a Cyclone V Avalon MM and with Qsys I've added a PIO. 

Well, Qsys setup the bar's size and I can't change it!! :( 

 

 

I need to change Bar's size because in file altpcietb_bfm_driver_avmm.v (inside there's a fuction whose name is fin_mem_bar) needs it  

to target memory on BAR with a size at least 4kb big and Qsys configurate my desing with a BAR's size of 1kb

 

 

So, I ask you this: 

How can I change the BAR's size in Qsys to size of 4kb o more? or How can I change BAR's size in file altpcietb_bfm_driver_avmm.v to least 1kb size?? 

:confused::confused:
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Valued Contributor III
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If you read the user's guide for the PCIe Avalon-MM core it tells you that the BAR size is not configurable. The BAR has to be connected to something and Qsys figures out the BAR size from that. Seems a weird way to handle it but that's the way they did it, at least for Arria 10. In my case I just wanted to export the BARs from Qsys into my logic, but if you do that the BAR size defaults to 0. You have to put some kind of Qsys Avalon-MM bridge between the BAR and the outside world. I'm using the Avalon MM Master Translator. I set the address width in the Master Translator configuration and Qsys figures out the BAR size from that. This has worked fine for me so far.

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Valued Contributor III
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Thanks for reply!! 

 

I've followed your advice and it works!!...... thank a lot!! 

 

Well, I've got you another questions about your method. 

 

1.- When you issue a PCIe's TLP you catch the data in RxmWriteData ???  

 

I ask you this because I'm trying to simulate a PCIe communication using Qsys' Test bench make me.  

There is a file where I can set a PCIe's TLP and issue it to my endpoint. 

Inside of that file the test bench issue a TLP to write a memory and next read that memory. 

 

I've issued next data 11111110000000000000000000000011  

 

I should watched in RxmWriteData my data, but I can't watch it (I watch another datas). 

But when I read data from my memory I can watch it (I watch it in RXMReadData). Futhermore, my test bench tells me by Modelsim's console "Target Write and Read compared okay", So I think that I've issued my data correctly, but I don't know why RxmWriteData doesn't show my data.
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Valued Contributor III
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sxmg92 - 

 

I agree that if you issued a write to the endpoint the data should come out on RxmWriteData for the BAR targeted by the write. Do you have more than one BAR? 

 

I did not simulate the endpoint so I'm not familiar with the test bench produced by Qsys.
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Valued Contributor III
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rsefton  

 

 

Thank for reply!! 

 

Yes, I've just got one BAR ..(BAR0) 

 

I send you a image of my Qsys wired. 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13604  

 

Inside, I've conected BAR0 to "avalon mm master translator" ( specifically in his port avalon_anti_master_) and I've conected master port of "avalon mm master translator" to tx port of my PCie avalon MM.... (please watch my image). 

 

Friend, I've got another question for you 

 

When you issue a TLP to PCIe wired or link (outside of interface) , Do you use Tx port of PCIe avalon MM (I refer, if you go to all interface signal of Tx such as TxsWrite, TxsRead, and so on....and you directly setup it) ???  

or Do you use "Avalon MM Master Translator" to send data to Tx and then Tx alone issue PCIe TLP to outside of interface?? 

 

Thank for your helping!!
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Valued Contributor III
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rsefton 

 

Please, Could you tell me how to issue from your PCIe's interface (PCIe Avalon MM interface) to PCIe link (outside from interface)??? 

 

Do you set Tx interface or any register?? 

 

Thanks for reply
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Valued Contributor III
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--- Quote Start ---  

rsefton 

 

Please, Could you tell me how to issue from your PCIe's interface (PCIe Avalon MM interface) to PCIe link (outside from interface)??? 

 

Do you set Tx interface or any register?? 

 

Thanks for reply 

--- Quote End ---  

 

 

Yes, the Tx interface is used to initiate transactions on the PCIe bus. 

 

If I understand what you said above, you have the BAR0 master AVMM interface connected to the Tx slave interface (through a AVMM master translator)? What are you trying to accomplish with that?
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Valued Contributor III
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This is a fyi follow-up on what I posted above about using the Avalon-MM Master Translator to export a PCIe BAR from Qsys. I exported two BARs (so far): One is non-bursting and is used for FPGA register accesses. The second supports bursting and is used for DMAs between FPGA memory and host memory. The non-bursting BAR worked fine with the Master Translator, and the bursting BAR worked fine with a burstcount of 1. But when trying to do bursts > 1 the burstcount coming out of the Master Translator was always 0, which is not a legal value. After going through local Altera support it was recommended that we use the Avalon-MM Pipeline Bridge to export the BARs instead of the Master Translator. In fact Altera said this: 

 

"Customers are not really encouraged to use the Avalon-MM Master Translator component, that's an internal Qsys fabric component that the fabric generators build into the generated interconnect. Customers should generally avoid anything in the Qsys Interconnect group unless they really know what they're doing. That's why these things aren't documented, they aren't expected to be generally used." 

 

Today I replaced the Master Translators with Pipeline Bridges and our bursting BAR is now working great. 

 

I also learned from Altera that Qsys Pro (in Quartus Prime Pro) allows PCIe BARs to be exported directly. From Altera: 

 

"If you’re using Qsys Pro, you can instantiate the IP core without a system and manipulate the system-info parameters which control the interfaces in the “exported interfaces” tab. In the case of the PCIE you’d want to set the max slave data width parameter which will feed into the PCIE’s AVMM interfaces. In the end you’d end up with a single .ip file configured as you want it. 

 

In Qsys standard, you’re stuck with the pipeline bridge and setting up a system to configure them to work as expected." 

 

Just wanted to pass this information along.
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