Character Register

[Altera_Forum]

Hi, (forgive me if I am posting in the wrong section) I am new to the VHDL programming language and I am currently working on a project (laser Pointer Projector) using the Altera DE2 board to implement this. The project is meant to receive a user input of a character/letter form a ps2 keyboard and display/project the Character/letter in dot matrix form via a laser pointer/diode. 

 I have come stuck with the comparing the keyboard scancode and generating a pulse sequence for the laser diode. The code seems to output the last statement and ignores the conditions in the code. Below is part of my register code in VHDL with comments for explanation.   Could anyone advise me on a different way of doing this or point out what I am doing wrong please.   LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;   entity reg is  Port ( scancode : in STD_LOGIC_VECTOR (7 downto 0);  laser : out STD_LOGIC_VECTOR (7 downto 0)); end reg;    architecture Behavioral of reg is  Signal char : STD_LOGIC_VECTOR (7 downto 0);    begin    process(scancode)  begin    case scancode is    WHEN "01000101" => -- scancode for the number 0  laser <= "11000001";   WHEN "00010110" => -- scancode for the number 1  laser <= "11110001";   WHEN "00011110" => -- scancode for the number 2  laser <= "10101100";   WHEN "00100110" => -- scancode for the number 3  laser <= "01100011";   WHEN OTHERS => -- when no scancode present  laser <= "11111111";  end case;  end process;  end Behavioral;   This code is a modification of displaying the number on a seven seg display. However, using this logic (code above), and shifting the laser vector through a shift register it ignors all conditions and pulses the laser diode in accordance to the last statement ( laser <= "11111111")   Any help on this would be appreciated. Thanks in advance.

[Altera_Forum]

Hi, 

I did not directly find any failure, but nevertheless; I would recommend to programm clock synchronous. This would ensure the case condition is evaluated every clock cycle and the "scancode" is read clock synchronous into the process. This excludes conditions with the vector scancode changing (asynchronous) and the Process being currently executed (due to change in scancode) does not "detect" the final stabilization.. (the 8 Bits of "scancode" vector may not change at same time...)

[Altera_Forum]

--- Quote Start ---  This would ensure the case condition is evaluated every clock cycle and the "scancode" is read clock synchronous into the process. This excludes conditions with the vector scancode changing (asynchronous) and the Process being currently executed (due to change in scancode) does not "detect" the final stabilization.. (the 8 Bits of "scancode" vector may not change at same time...)  --- Quote End ---   Although writing clock synchronous logic is always recommended, in this case you won't have this problem. The process code is not executed like in a microprocessor, where this 'partial change' condition could happen. Instead, the HDL code will be synthesized as combinatorial logic: the process(scancode) condition is somehow virtual and the synthesized logic will evaluate scancode in a continuous way.  I'd rather suggest you change the case entries in this way:  WHEN std_logic_vector("01000101") =>  and so on. If this doesn't solve your problem, focus on the input scancode: is it really as expected? Are you sure it ever matches one of the required codes? Could the bit order be inverted?

[Altera_Forum]

Hi carlhermann and cris72 

 Thanks for the input, I will attempt both and give feedback.   Cris76 the scancode is generated from a ps2 keyboard and the keyboard control that I have generated works as i can display the character pressed on a seven segment display. The "scancode" vector in the code i have presented is the expected scancode for the respective key pressed.   Thanks again the feedback is appreciated.

[Altera_Forum]

--- Quote Start ---    I'd rather suggest you change the case entries in this way: WHEN std_logic_vector("01000101") =>  and so on.  --- Quote End ---     I have attempted this method but I get errors and it can not synthesis.   Error (10411): VHDL Type Conversion error at REG.vhd(27): can't determine type of object or expression near text or symbol "std_logic_vector"   I changed the code to;   process(scancode) begin case scancode is WHEN std_logic_vector("01000101") => -- scancode for the number 0 laser <= "11000001";  WHEN std_logic_vector("00010110") => -- scancode for the number 1 laser <= "11110001";  WHEN std_logic_vector("00011110") => -- scancode for the number 2 laser <= "10101100";  WHEN std_logic_vector("00100110") => -- scancode for the number 3 laser <= "01100011";  WHEN OTHERS => -- when no scancode present laser <= "11111111";   as recommended, am I doing something wrong? Do need to declare each scancode vector in the architecture?

[Altera_Forum]

Sorry, I missed a ' 

This is the correct syntax WHEN std_logic_vector'("01000101") =>

[Altera_Forum]

Try to use signaltap and see if what's coming is what you expect to come.

[Altera_Forum]

Thanks Cris, your correction allowed the program to synthesis and compile. My laser diode is still however pulsing the last statement of the case  

i.e. when others => laser <= "10101010"; I know it is pulsing this statement because when i change this vector it pulses according to this vector.   The simulation for this register simulates perfectly though.     --- Quote Start ---  Try to use signaltap and see if what's coming is what you expect to come.  --- Quote End ---     Could you please explain wat signaltap is (I am new to this).

[Altera_Forum]

Have you tried to comment out everything and add a simple laser<=scancode instruction?  

This will show you if there is some timing issue between the scancode change and when laser register is taken to the pulse generator. Infact, I'm concerned about your totally asynchronous code whereas laser register must feed some sort synchronous logic. I think you are sampling laser into a shift register to generate the pulses. My guess is that you sample it a little before scancode has settled, so you get an invalid code. You don't have the problem with the 7seg display since this is asynchronous, too.