Chipselect in Avalon Interfaces

[Altera_Forum]

Hi all, 

 I am getting used to using Quartus II and Qsys after being a long time Xilinx FPGA designer.  Question or request for clarification. Altera says in the Avalon Interface Spec that  "The chipselect signal is not necessary; Altera does not recommend using it."  I have a distributed architecture where several modules hang on the Avalon bus. I have assigned the memory map for each module and run a compilation without errors.  What I am not seeing is just how the memory map is applied to the distributed modules? I tried making the Avalon bus address the full 32 bits thinking that Qsys would use the upper addresses to partition the memory map assignments, but ran into problems. The memory map thought each module occupied the full 32 address bits and balked. So, I reduced the Address bus back to just the bits for that module.  I can see assigning Chipselects in the master and connecting each module to it's own chipselect, but this seems to fly in the face of Altera statement above about chipselects not being necessary.  Unfortunately, I am one of these guys that can't rest without a good understanding, and this one confuses me.  Any comment?  Thanks

[Altera_Forum]

Qsys generates a interconnection fabric which filters "read" and "write" signals from the masters accordingly to the address and the address map. 

 So, a slave only sees "read" and "write" signals intended for them, not for other slaves.  No clue what the chipselect signal was even intended for.

[Altera_Forum]

Thanks, that would make sense. By the way, is that the difference between read and say read_n? The latter being directed by memory assignments.

[Altera_Forum]

read is active high, read_n is active low. 

I think the fabric will also take care of it -- never used it.

[Altera_Forum]

You are correct the fabric takes care of the read vs read_n. It is so it will be easier for the user if they prefer negative control over positive. Just don't use both :)