Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Choosing a FPGA

Altera_Forum
Honored Contributor II
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Hi, 

I am using a FPGA with a DDS board (AD9910). The DDS board has a parallel port where I can send a 16bit word every clock pulse. The DDS parallel port can latch onto data every 4ns. So far I have been using the deo-Nano board to send data every 20ns but now I want to maximize on the speed of data transfer. I would also like to store a list of 16bit words to the SDRAM on the board and then read it out every 4ns from the SDRAM to the GPIO headers. From what I have read on the deo nano so far, it seems that reading data every 4ns from the SDRAM on the deo nano board is not possible. I would be very grateful if someone could direct me towards a board where such speeds are attainable or tell me if it's possible on the deo nano and what all timing considerations I should take into account.Also, I need a Thanks!
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Altera_Forum
Honored Contributor II
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You could try using on-chip memory instead of SDRAM to improve speed. M9K Blocks max speed is 315 MHz but more can be achieved using LEs. 

With Cyclone V MLAB you can reach 420 MHz but Cyc IV should be enough if you don't have a lot of logic between DDS port and memory.
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