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Clock Constraints with PLL

Honored Contributor II

A very basic question, (I am using Altium for design input but please answer as if I am using Quartus) 

I have a design that needs some logic that runs at 96MHz. I have an embedded processor that can run as slow as 40MHz. 

When I specify clock constraints using 2 separate clocks, the timing report says something like 196MHz and 56MHz. 

When I change the clock input to use an ALTPLL component running from 8Mhz in and generating 96MHz and 40MHz respectively the report no longer shows the two separate clock constraints even though I have left them in, and the external single clock says 60MHz, which is obviously impossible given the PLL outputs. 


My question is, when you use a single PLL with 2 outputs that do not have linked timing requirements, do the tools still link the timing together. That is, will the max frequency of the logic part be reduced because of the processor part. 

Why are the max clock speeds not being reported when using the PLL? 

Should I use a single external clock to drive 2 PLLs, stick with 2 separate clocks, or is my original concept of 1 pll driving 2 independant cloks ok? 


I have a similar design using a single clock driving a PLL with 2 outputs, but the logic speed is not so crucial, and the post PLL clock output speeds are reported. 


I am using a Cyclone IV with quartus 9.2 pro. 


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Honored Contributor II

When using a pll you should only have one input clock constrain, for your 8MHz input, with the create_clock command. Then for the two other clocks, either use the derive_pll_clocks command to create automatically, or a pair of create_generated_clock if you want to do it manually. Then you should see one line per clock in the timing report. 

There is nothing wrong in using one PLL to generate both 40 MHz and 96 MHz.