Clock connection problem of PRBS7 pattern

[Altera_Forum]

Hi, I'm FPGAs begginer.  

My device is Stratix IV GX. I tried to get PRBS7 pattern from the device using <StratixIV GX Transceiver Signal Integrity Demonstration Version 9.1> program, and sended it to oscilloscope. I connected a input with channel 0 (J30 in board) which can make the pattern and connected a trigger with clk. In this step, I tried all clks. I also tried to use spread spectrum clk. However, I can't find a clk which has appropriate frequency.  Program says that data rate of channel 0 is "20*clk freq".    In the board, there are IO clk output (J16, J17).  How can I use these clks?   How can I make the appropriate clk? Do I have to program a clk? So, how can I make that clk frequency?

[Altera_Forum]

Tell us more about the hardware platform you're using. Is it a development kit? Your PRBS7 generator should simply need a clock, any clock, to drive it. We just need to figure out what clocks your hardware has. Then we can get things up and running... 

 Regards, Alex

[Altera_Forum]

So, you need to drive your PRBS7 logic with a clock. I suggest you use (in the first instance) the 50MHz clock sourced from Y2. This source is driven into the U33 (the Stratix IV FPGA) on pin AR22. That should result in you seeing something appropriate on your oscilloscope. 

 With your project open in Quartus, select 'Assignments' -> 'Pin Planner'. Find the row with your clock input signal in. Under the 'Location' column type 'AR22'. This will connect the 50MHz clock source to the clock that drives your logic.  J16 & J17 are there to allow clocks to be driven OFF the board. As specified in the data you provided, these are driven from FPGA pins M20 & L20 respectively. Any signal you connect from your logic to these pins will appear on the connectors.   --- Quote Start ---  Program says that data rate of channel 0 is "20*clk freq"  --- Quote End ---   What program? And what are you trying to achieve?  Regards, Alex