Hello Dear Friend,
I have a design that is now working, but I would like to have some help to improve it. Before asking anything, I would like to make a context like the following description.
I am using the ALTDDIO for reading a double data rate from an IC. Then, a FIFO registers the output of the ALTDDIO (I have a bus of 12 bits). When I need the data, I just read it from the FIFO. I think this is the correct way to design when there are different clock domains. Well, I can now describe the actual problem...
I have designed my project using the method of trial and error. Then, I perhaps ended up in a non-conventional design. I am getting an external clock source and feeding it into an ALTPLL IPCORE. Then, I created two output clocks as clones of the input source. One output goes to the ALTDDIO clock, and the second goes to the FIFO. This was the only way I found to do the design to work (and it works fine).
On the other hand, the direct clock source connected to the ALTDDIO and FIFO just fails. My conjectures point to a better solution, such as using clock constraints. If this makes sense, can someone tell me how to do it? I have read some tutorials, but it is very confusing. I think that using a direct source to feed the components do not ensure the same clock edge. Perhaps, using ALTPLL uses PLL to ensure timing. But, I prefer to use and .SDC file instead of including an IPCORE.
You have mentioned that the direct clock source connected to the ALTDDIO and FIFO just fails. May I know whether it is a compilation error or timing violation?
Thanks for your interest in helping me. I was using a signal tap to check signals. Then, I used an oscilloscope to check output signals, and it was working. It is all working fine now. Thanks!