Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Clock divider

Altera_Forum
Honored Contributor II
‎07-22-2009 07:39 PM
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Hi. I would like to know how is the best way for implement a clock divider on a Cyclone II FPGA. My application is for audio, and need to work in a frequency of 44.1 kHz. 

 

Thank's 

 

Leandro
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Altera_Forum
Honored Contributor II
‎07-22-2009 08:14 PM
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With some prayer the following thread may help 

http://www.alteraforum.com/forum/showthread.php?p=25505#post25505
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