Clock generated from normal IO has a DC offset

[RLee42]

I tried to use general IO to generate a clock for other ICs. This generated clock is from the PLL which is fed in with a crystal oscillator.  When I measured this clock at the output pin, I found that the frequency is correct as I expected, but the voltage is not correct. 

This pin is configured as LVCMOS-3.3v, so the Voh/Vol should around 3.2v/0.1v, but from this image below, the Max/Min voltage is 2.28v/1.12v. It has an above 1v DC offset which makes trouble for other ICs who use this clock. 

My question is how to reduce this DC offset to make the IO generated clock meet the LVCMOS standard.

[AminT_Intel]

Hello,

Are you using Intel FPGAs? May I know which device and what is your OPN?

Thanks. 

[AminT_Intel · Accepted solution]

Hello,

Is there any update from your end? I will need to close this case in 3 days if there is not respond from you.

Thank you.